i just gave it a thought and have a feeling that it will work.
During simulation write a testbench which enables only the switching / triggering of this specific logic cone and export the activity information file.
You can also use the entire design testbench for a long period and huge a specific timing scope where only this logic work and export activity files based on time scopes.
Now read this file in the synthesis tool which help you estimate the power.
I am aware of RTL compiler that reads multiple activity files and also helps estimate power which correlates till synthesis netlist only but for big designs it helps share feedback back to RTL team
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i just gave it a thought and have a feeling that it will work.
During simulation write a testbench which enables only the switching / triggering of this specific logic cone and export the activity information file.
You can also use the entire design testbench for a long period and huge a specific timing scope where only this logic work and export activity files based on time scopes.
Now read this file in the synthesis tool which help you estimate the power.
I am aware of RTL compiler that reads multiple activity files and also helps estimate power which correlates till synthesis netlist only but for big designs it helps share feedback back to RTL team