Power Efficiency Calculations of Switched Capacitor DC-DC Converter

Tunelabguy said:

Are you driving the gates so that they are sometimes forward biased? If so, that is your problem. The gate of an enhancement mode FET must always be driven to either the same voltage as the source pin, or else in the direction of enhancement with respect to the souce pin. If you can't ensure that, the gate will take current, and it is not considered "leakage". It is considered forward biased, and it is improper design.

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The input to the gate is a clock signal. the clock signal is square wave [0V , Vdd] vdd is the maximum voltage value in the circuit which is the same as the source voltage. Bulk is connected to vdd. Do you mean by forward biased that it is working in the linear region?! I want to work as a switch-->sat region. Can you suggest a way to fix the problem?!

I agree that there are apparently leakage currents in the idle phase between clock edges. I presume, they occur due to non-ideal behaviour of 65 nm transistors and in so far aren't particularly related to the switched capacitor circuit.

Which parameter is changed between the four waveforms so that different amounts of leakage are measured?

DimaKilani said:

The input to the gate is a clock signal. the clock signal is square wave [0V , Vdd] vdd is the maximum voltage value in the circuit which is the same as the source voltage. Bulk is connected to vdd. Do you mean by forward biased that it is working in the linear region?! I want to work as a switch-->sat region. Can you suggest a way to fix the problem?!

Click to expand...

I do not mean the gate is operating in the linear region. One way I have seen this handled is to AC couple the gate drive and use diodes to clamp the voltage between the source and Vdd (for NMOS) or between the source and 0v (for PMOS). The point is that the effect of gate drive on the FET should always be viewed as a voltage with respect to the source. The gate pin does not care where ground it. It only cares whee the source pin is, and it figures its response based only on that. When the source is not at 0v (for NMOS) or +Vdd(for PMOS), the gate needs to be level-shifted, either with an AC-coupled DC restoring circuit as I mentioned, or by some other means. I am not familiar with what common techniques there are for achieving this in switched-capacitor converters. You will have to find that out from someone else.

FvM said:

I agree that there are apparently leakage currents in the idle phase between clock edges. I presume, they occur due to non-ideal behaviour of 65 nm transistors and in so far aren't particularly related to the switched capacitor circuit.

Which parameter is changed between the four waveforms so that different amounts of leakage are measured?

Click to expand...

I just put this transistor with multiple transistors in a switched capacitor circuit and i notice the leakage current !