The term gate "leakage" involves an average current through the gate. Do you actually see a leakage current? As far as I remember your previously posted circuit and related measurements, you have been reporting pulsating currents but not specifically leakage currents.
Yes, I see a gate leakage. When I measured the current across the transistor, large amount of the source current goes to the gate.
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be aware that i replaced the switches by NMOS and PMOS transistor with 65nm process technology. This means that the circuit is not ideal. Yes, I added a capacitor load at the output in order to reduce the voltage ripples.
As you mentioned when explaining the operation, in the 1st phase, the input current (on current of the switched capacitor) will charges the capacitors. in the 2nd phase, the supply will disconnected from the capacitors, and the then the capacitor will discharge into the load. This means that the input current (off current of the switched capacitor) should be almost zero because the supply is disconnected in the 2nd phase. But what i got in my simulation is that there is an off current which is near to the on current that is in microA. I tried to figure out the problem why the off current is high. So, i measured the source, drain, gate and bulk current and I found there is a leakage current goes from a source to the load. I dont know how to solve such issue.
The current in the 2nd phase should be almost zero because the supply is disconnected. Am I right ?
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be aware that i replaced the switches by NMOS and PMOS transistor with 65nm process technology. This means that the circuit is not ideal. Yes, I added a capacitor load at the output in order to reduce the voltage ripples. The circuit works properly and I tested each voltage node and it gives me the expected voltage as what I analyze it theoretically.
As you mentioned when explaining the operation, in the 1st phase, the input current (on current of the switched capacitor) will charges the capacitors. in the 2nd phase, the supply will disconnected from the capacitors, and the then the capacitor will discharge into the load. This means that the input current (off current of the switched capacitor) should be almost zero because the supply is disconnected in the 2nd phase. But what i got in my simulation is that there is an off current which is near to the on current that is in microA. I tried to figure out the problem why the off current is high. So, i measured the source, drain, gate and bulk current and I found there is a leakage current goes from a source to the load. I dont know how to solve such issue.
The current in the 2nd phase should be almost zero because the supply is disconnected. Am I right ?
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In looking at that circuit, it seems that with ideal no-loss switches, the efficiency would approach 100% for loads approaching zero Amps. It looks like it is designed to produce a voltage that is exactly 2/3 of the battery voltage. The lower two capacitors will both charge up to 1/3 of Vbatt and the upper capacitor will charge to 2/3 of Vbatt during phase 1. Then during phase 2, the lower two capacitors will be connected in series to produce 2/3 Vbatt and this combination will be placed in parallel with the upper capacitor, which also is at 2/3 of Vbatt. Everything is so well balanced that no current needs to flow when there is no load.
Notice also that this circuit, all by itself, does not produce a DC voltage. It still needs some filter caps. Since you have not shown any way for power to be wasted (other than imperfect switching), I don't see how you expect to find any meaningfull calculation of efficiency with a simulation.
be aware that i replaced the switches by NMOS and PMOS transistor with 65nm process technology. This means that the circuit is not ideal. Yes, I added a capacitor load at the output in order to reduce the voltage ripples. The circuit works properly and I tested each voltage node and it gives me the expected voltage as what I analyze it theoretically.
As you mentioned when explaining the operation, in the 1st phase, the input current (on current of the switched capacitor) will charges the capacitors. in the 2nd phase, the supply will disconnected from the capacitors, and the then the capacitor will discharge into the load. This means that the input current (off current of the switched capacitor) should be almost zero because the supply is disconnected in the 2nd phase. But what i got in my simulation is that there is an off current which is near to the on current that is in microA. I tried to figure out the problem why the off current is high. So, i measured the source, drain, gate and bulk current and I found there is a leakage current goes from a source to the load. I dont know how to solve such issue.
The current in the 2nd phase should be almost zero because the supply is disconnected. Am I right ?
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here i use the pmos as a switch and i connected a capacitor to it. (note: V/15/MINUS) is the input current.
There is no leakage current in this case when both pmos on and off. but in my Switched capacitor circuit, there is a leakage although i use same transistor size and capacitor.
But i noticed that the input current has negative and positive values, it there any reason for that?
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becuase you mentioned something about the ideal switches. I designed before a switched capcitor with a gain of 1/2 with ideal switches. and I would like to share it with you.
and the results are expected where the input current when S1 is on in microA, when when S1 is off which means the off current is in femtoA.
but when replacing the ideal switches with the pmos and nmos transistors, the off current becomes in uA (uA=microA).
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Any ideas ?
Your help is highly appreciated