hongzeng
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Hi, I have some doubts about the power dissipation of SRAM and DRAM.
One idea is SRAM will consume more because the structures of SRAM is more complex with more transistors like 6 and DRAM maybe 3 or even 1 Transistors.
One debate is DRAM has to refresh the cell in a period and that consumes a lot of dynamic power.
Which one is more close to the reality? Or it depends on the frequency of the DRAM working or the frequency of Write or Read instructions?
BTW, how is the cap inside DRAM built? is it a MOSCAP(That's what they use in analog IC no idea if in the digital IC is the same)?
Thanks guys~~
One idea is SRAM will consume more because the structures of SRAM is more complex with more transistors like 6 and DRAM maybe 3 or even 1 Transistors.
One debate is DRAM has to refresh the cell in a period and that consumes a lot of dynamic power.
Which one is more close to the reality? Or it depends on the frequency of the DRAM working or the frequency of Write or Read instructions?
BTW, how is the cap inside DRAM built? is it a MOSCAP(That's what they use in analog IC no idea if in the digital IC is the same)?
Thanks guys~~