[SOLVED] Power bump connects to power stripes

Hello,

I intend to connect the power bumps to power stripes directly. Can I do this? or I need to connect power bumps to power cells (placed at IO area), power cells are connected to the power stripes?

Thanks so much.
Steve

You can connect bumps to stripes directly. Do not forget to add ESD protection (power cells or clamps ...) - see foundry DRM for details.

most likely you can, but ESD protection becomes your problem instead of being provided by the pad/IO ring

oratie said:

You can connect bumps to stripes directly. Do not forget to add ESD protection (power cells or clamps ...) - see foundry DRM for details.

Click to expand...

Hello Oratie,

In this case, there is no voltage supply protection. I mean if we apply a supply voltage over the nominal level to the bump, that voltage level applies to the standard cells directly. So, the standard cells may operate at high voltage level. Is there any risk in this case? Is there any special power/ground bumps? Is there any difference between power/ground bumps and signal bumps?

Many thank.
Steve.

ThisIsNotSam said:

most likely you can, but ESD protection becomes your problem instead of being provided by the pad/IO ring

Click to expand...

Hello ThisIsNotSam,

For the chip operating at high frequency and consuming high power, it is difficult to draw the power supply from the I/O power pad at the IO area. As I know, the limit current of a power pad is 20mA (for TSMC HPC 28nm). If the chip consumes 800mA, we need at least 40 power pads. They occupied a large area in the IO ring. Could you have any suggestion?

Many thanks.
Steve.

Only 20mA? That doesn't sound right, it should be closer to 50mA. Double check the documentation, there are different numbers given for different routing scenarios. Typically the power IO cell has multiple overlapping pins on M3-M7. If you route all of them, you get more current delivered. Sometimes there is the possibility to route with AP directly for even more current.

But ok, let's say you can only get 20mA. Then the logical alternative is to mix area IO with periphery IO, meaning that some bumps in the middle of the chip are going to connect down to the core. This is perfectly fine, as long as you add clamp cells to protect your circuit against ESD. These cells are not area-free, they take some space, but they are absolutely needed. Otherwise there are no guarantees your chip will not burn when a human holds it in his hands.

stevenv07 said:

In this case, there is no voltage supply protection. I mean if we apply a supply voltage over the nominal level to the bump, that voltage level applies to the standard cells directly. So, the standard cells may operate at high voltage level. Is there any risk in this case? Is there any special power/ground bumps? Is there any difference between power/ground bumps and signal bumps?

Click to expand...

You shoud apply appropriate voltage to the bump connected to the standard cells (the power IO cells do not have any level shifter inside, only direct connection plus ESD protection). So, it is your fault if you apply higher voltage. There are no any differences between power and signal bumps. They are the same. For very big chips it is common practice to place power bumps across all chip.