amansingh2704
Newbie
I have few question regarding Gate Level Simulation.
1. what is difference between power aware netlist and non PA netlist.
2. Does Non PA netlist contains low power element such as clock gating, isolation, retention cells etc. ?
3. Do we run PA sim with SDF? In real chip we will have power as well as delays, so running PA+SDF makes more sense(my thinking)
4. Does STA engineer checks multi-cycle path and false path?
5. Once PA sim is completed, what do we check?
6. while running PA-GLS, if we forget to add power pin (vcc,vss) in UPF for a particular partition, we will get x in all outputs after simulation. is it possible to check and cure this issue after build is completed?
1. what is difference between power aware netlist and non PA netlist.
2. Does Non PA netlist contains low power element such as clock gating, isolation, retention cells etc. ?
3. Do we run PA sim with SDF? In real chip we will have power as well as delays, so running PA+SDF makes more sense(my thinking)
4. Does STA engineer checks multi-cycle path and false path?
5. Once PA sim is completed, what do we check?
6. while running PA-GLS, if we forget to add power pin (vcc,vss) in UPF for a particular partition, we will get x in all outputs after simulation. is it possible to check and cure this issue after build is completed?
