Power Amplifier with BJTransistors

[albus]

**broken link removed**

The above circuit is supposed to be a push-pull amplifier and I'm supposed to find the dc currents of the transistors for Vout=0. But i just can't do it. According to my calculation Q7 and Q6 will have the same collector current and therefore Q5 will also have the same collector current( of course this is an approximation I left out the base currents). So if Q5 is in forward active mode then Q2 is in cut-off and since Vout=0 Q1 will also be in cut off. Now there is the contradiction Q1 can not be in cutoff because Q5 is in forward active mode.

Am I missing something here ?

 

[Miguel Gaspar]

Well . . . . .
When there is no input signal Vsin=0, Vout = 0 that means that Q1 and Q2 are in active mode.
Q4 and Q3 is a darlington pair but in this case give a 2Vbe that gives a Q1 and Q2 the bias point and set the bias point to active.
Now when Vsin increases or going positive . . .Veb of Q5 decreases . . . so Q1 decreases and Q2 increases. IE1 decreases and IE2 increases so a current flowing fron Rl, and negative voltage.
Now when Vsin decreases or going negative . . .Veb of Q5 increases . . . so Q1 increases and Q2 decreases. IE1 increases and IE2 decreases so a current flowing from source trough Q1 and Rl, and positive voltage.

I expect that I could explain. If not please let me know

 

[albus]

I didn't understand how Q1 and Q2 are in active mode when Vout=0. Ie7 and Ie6 will be automatically 180 uA. The darlington pair and Q5 will let this current flow, won't they ? So the emitter voltage of Q5 will be around 0.6-0.7 V, which means that the base voltage of Q2 will be the same and since Q2 is pnp and the base voltage will be bigger than emitter voltage Q2 will be in cutoff?

Could you explain how Q1 and Q2 will be in active mode ?

 

[Miguel Gaspar]

iF YOU HAVE TWO

---------- Post added at 21:17 ---------- Previous post was at 21:05 ----------

if all the current flow trough Q1 and Q2 that means IcQ1 = IcQ2 so VceQ1 = VceQ2 both transistors are working but VeQ1 = 0. Perhaps you could see if you rplace transistors Q1 and Q2 by two resistors of the same value, so the point in the middle of the resistors is 0V.
Q5 if adjusted so Vout is 0V and Q1 and Q2 are in active mode, that implies Vbe1 ≈0.7 and Vbe2≈0.7, that is the function of Q3 and Q4.
Your seconf consideration are wrong. If VbQ5 increases, VebQ5 decreases. IcQ5 decreases so VbeQ2 increases. . . . and so on.

 

[KerimF]

It all depends on the voltage Vce on Q3 which is almost 2*Vd (Vd=diode forward voltage). So when Vin=0 Q1 and Q2 are both near cutoff or near conduction if their Vbe is a bit higher ot lower than half of Vce of Q3. But even if there is a small current going out of Q1 emitter it is absorbed by the emitter of Q2. The result Vout=0 in both cases.

This is how I see, in the least.

Kerim

 

[RCinFLA]

The DC output voltage when input sinewave is zero will be two diode drops above ground. Specifically the Q5 Vbe plus Q2 Vbe.

The Q3/Q4 circuit sets the bias current for the output devices. If all the devices are exactly the same. Q4 will be drawing roughly 0.6/40k or about 17 uA of the 180 uA created by the top current mirror. (specifically Vbe of Q3/40k plus base current of Q3 to produce 180uA - Q3 Vbe/40k) The rest of the current (180-17 uA) must flow through Q3. You can take the ratio of these currents (roughly 10:1) to determine Q3's and Q4's Vbe's. The total voltage (about two diode drops) will determine the idle current in the two output devices Q1 & Q2.

Again, if all the devices are exactly the same there will be an associated relationship between each of their Vbe's and the emitter current. By finding the exact values of Q3 and Q4 Vbe's you can find out what Q1 and Q2 idle current must be.

The AC gain of the amp is two emitter followers in cascade, so something less then a voltage gain of 1.

 

[mtwieg]

I think this is kind of a flaw in the problem (is this homework or something). For the amplifier to operate correctly there needs to be some DC bias between Vin and Vout. you can still analyze it, but it's not a useful analysis... I think maybe you're supposed to assume that your input is biased such that all the transistors are active.

 

[RCinFLA]

It is not a good design. There are a couple of issues, here are some hints.

With the two diode drop biasing having the first device Q4 having a tenth of the current through the second device Q3 the output stages will mirror to less then 180 uA of idle bias.

Then there is the problem with the two diode offset to output junction set by the Q5 + Q2 Vbe's. With 2k direct coupled load that will be 1.25v/ 2000 or about 625 uA of bleed off supplied by upper device Q1. That will create a greater Vbe (based on 625 uA Ie on Q1) which eats up much of the two diode biasing of Q4 & Q3, resulting in Q2 output device being close to shut down.

 

[albus]

I didn't design it actually, I'm just trying to analyze it. But the question still remains unsolved for me, although I think mtwieg understood what I was trying to say.

@RCinFLA

I've done all those calculations, but there is just one problem if Q3 and Q4's currents are 17 and 163 uA respectively, then the total current must flow through Q5. The base voltage of Q5 is 0 when the input signal is zero, so the emitter voltage of Q5 is around 0.7 V. Here comes the question. How can Q2 let the current flow, when its emitter voltage is 0 (Vout=0) and its base voltage is 0.7, in other words when it is in cutoff?

 

[FvM]

Specifying Vout = 0 implies Vsin must be about -1.2V. It's not stated in the problem, but necessary anyway. So the base voltages of Q1 and Q2 have to be symmetrical centered around zero. There's no feedback, so you have to assume, that Vsin is exactly biased to a voltage, that Vout = 0 can be met. Obviously, it can't be zero.

The problem doesn't disclose the assumptions for the calculation. A Vbe forward voltage for a particular collector current has to be assumed, also a current gain, and I guess an exponential Vbe slope of 60 mV/decade.

 

[albus]

Oh okay now I get it. I always left out the AC signal when i was analyzing. Thank you all so much.

 

[RCinFLA]

Somehow I don't think the instructor realized the 1.2 volt offset. A grounded sinewave voltage source has zero dc average in any convention. We asked for Vout = 0 I bet instructors interpretation is zero AC drive and zero AC out.

I would take it as drawn.

That would give you near two diode drops of positive voltage at output. Q1 current will be what the 2k load resistor demands, about 600 uA. Q2 will be near cutoff, maybe a microamp or two.

If 2k output load is removed, both Q1 and Q2 will have about 50 uA of idle bias. You can work the simultaneous equations to get the exact number. Again, the primary reason for reduced idle bias is the near ten to one ratio'g of the two bias diodes 180 uA.

Assuming there is a -1.2 v bias on the input voltage source is more a stretch of imagination as the bias voltage needs to be exactly what the two diode drops of Q5 and Q2 to get exactly zero volts at output node. When you do get the negative input bias correct there will be the approximately 50 uA idle through output devices.

 

[FvM]

Somehow I don't think the instructor realized the 1.2 volt offset. A grounded sinewave voltage source has zero dc average in any convention. We asked for Vout = 0 I bet instructors interpretation is zero AC drive and zero AC out.

You're free to assume what you want for an unclear respectively inconsistent problem. But it's arbitrary as well to assume zero AC drive or zero AC output voltage, nothing has been said about AC levels as far as I see. So I still think, that understanding Vout=0 as a DC specification for a DC problem is at least one reasonable assumption.

 

[RCinFLA]

You're free to assume what you want for an unclear respectively inconsistent problem. But it's arbitrary as well to assume zero AC drive or zero AC output voltage, nothing has been said about AC levels as far as I see. So I still think, that understanding Vout=0 as a DC specification for a DC problem is at least one reasonable assumption.

Assuming Vout = 0 as DC level would be changing the schematic and adding a critical negative voltage offset input. I would let it play as shown, it also makes the solution easier.