power amplifier PAE at compression

[jayce3390]

Hi RF experts,

I am posting here a picture of the simulated PAE of my 50 W power amplifier. The PAE behaves strangely close to the saturation.



Does anyone have seen this before?
Could be related with stability?

 

[ge]

Do I see correctly that the trace is folding over on itself? That's impressive... but you probably don't think so. I've never seen anything like this before. Can you supply schematic? What type of amplifier is this? Is this a linear, non-linear or ... simulation?

 

[jayce3390]

Do I see correctly that the trace is folding over on itself? That's impressive... but you probably don't think so. I've never seen anything like this before. Can you supply schematic? What type of amplifier is this? Is this a linear, non-linear or ... simulation?

Yes you see correctly.

This is a non linear HEMT GaN 50 W amplifier operating from 10MHz to 700 MHz.

 

[BigBoss]

Yes you see correctly.

This is a non linear HEMT GaN 50 W amplifier operating from 10MHz to 700 MHz.

View attachment 81699

Simulation setup has some erros.90 degree Coupler and Combiner circuits have been defined for RF frequencies, at DC they may be trouble by definition..
That's why supply circuits should be added externally for a proper bias.

 

[vfone]

The PAE plot is correct, maybe the fall at the end is a little bit accentuated.
Because PAE=(Pout-Pinp)/Pdc when the PA goes near saturation and over, when you increase the Pinp the Pout remain the same and the PAE goes down.

Just search the net for Power Added Efficiency images and you get similar plots.
**broken link removed**

 

[jayce3390]

The PAE plot is correct, maybe the fall at the end is a little bit accentuated.
Because PAE=(Pout-Pinp)/Pdc when the PA goes near saturation and over, when you increase the Pinp the Pout remain the same and the PAE goes down.

Just search the net for Power Added Efficiency images and you get similar plots.
**broken link removed**

vfone, if you zoom in you ll see that the PAE fall is not what you usually get, it is different from the link you gave me. The PAE goes down but on the other side .

- - - Updated - - -

Simulation setup has some erros.90 degree Coupler and Combiner circuits have been defined for RF frequencies, at DC they may be trouble by definition..
That's why supply circuits should be added externally for a proper bias.

BigBoss, i did not post the supply circuit, here it is. I don't have any 90 degree coupler at the output, it is a balun (180 degree. )

 

[BigBoss]

BigBoss, i did not post the supply circuit, here it is. I don't have any 90 degree coupler at the output, it is a balun (180 degree. )

I'm saying that you supply MOS through Balun circuits but these circuits are effectively defined for RF/AC signals that's why , your simulator will do an interpolation at DC and the results may be erroneous.
Consider the circuits equations are limited by frequency of these kind of circuits.

 

[jayce3390]

I'm saying that you supply MOS through Balun circuits but these circuits are effectively defined for RF/AC signals that's why , your simulator will do an interpolation at DC and the results may be erroneous.
Consider the circuits equations are limited by frequency of these kind of circuits.

ok, so the computed DC power may be wrong.

Do you have any idea to compute PAE properly with this kind of circuit?

 

[BigBoss]

ok, so the computed DC power may be wrong.

Do you have any idea to compute PAE properly with this kind of circuit?

I post a picture to you give an idea...

 

[jayce3390]

I post a picture to you give an idea...

Thanks BigBoss, in the DC decoupling circuit I have a 1uH inductor for the drain, and in my output circuit i have bypass capacitors. Is it similar to the picture you post? I believe DC_feed component from ADS is actually a 1uH inductor.

 

[BigBoss]

Thanks BigBoss, in the DC decoupling circuit I have a 1uH inductor for the drain, and in my output circuit i have bypass capacitors. Is it similar to the picture you post? I believe DC_feed component from ADS is actually a 1uH inductor.

DC block is an ideal component so that inductance value-for instance- 1H
Coupling component is also an ideal element that has-for instance- 1F

There isn't any constraint to use these component.Af

 

[jayce3390]

DC block is an ideal component so that inductance value-for instance- 1H
Coupling component is also an ideal element that has-for instance- 1F

There isn't any constraint to use these component.Af

I tried to replace the bypass capacitors I have and the inductors by these components and the PAE trend is the exactly the same. My conclusion is that the DC power is probably properly computed.

 

[BigBoss]

I tried to replace the bypass capacitors I have and the inductors by these components and the PAE trend is the exactly the same. My conclusion is that the DC power is probably properly computed.

If we logically consider your PAE curve, can the effciency be 0% ?? at 15dBm Output Power ??
There are still erroneous points..

 

[mtwieg]

Circuitry aside, there's obviously something wrong with the way the program reports its data. There's no way the plot should "fold" back on itself; it has to be a valid function. That is, of course, unless the simulation is doing something exotic like sweeping power up and down to give hysteresis effects, but I doubt that's the case.

 

[jayce3390]

If we logically consider your PAE curve, can the effciency be 0% ?? at 15dBm Output Power ??
There are still erroneous points..

Thanks for your contribution, this is a a 50 W amplifier, 15 dBm output power is very far from saturation, I guess the efficiency is very bad at such power level, it is more than 30 dB output back off, does it make sense?

 

[johnjoe]

it makes sense, compared to dc power consumption the output power level is obviously quite low. Can you may be also plot Pout and PAE vs. Pin? Do you see there the same strange curve?

 

[jayce3390]

I plotted Pout and PAE vs Pin :

 

[johnjoe]

Both graphs look quite good, so i think it is a plotting error by ADS!

Beside: For which frequency is the amplifier?

 

[BigBoss]

I plotted Pout and PAE vs Pin :
View attachment 81975

Now it looks like correct.

 

[jayce3390]

I measured S parameters of the built PA and got the S11 I attached. I tried to tune the input matching network in order to improve the matching at low frequency 9between DC and 200 MHz). I could not find any better solution that what I post here. Does anyone have an idea according to the related circuit topology I show here?