ansonyeap
Member level 2
Recently, I design a class E power amplifier circuit by referring to Mr Nathan O. Sokal's article which is "Class E RF Power Amplifier". I follow the design equations and also the conventional class E power amplifier circuit (single stage) as stated in the articles mention before. The simulator that I used is cadence virtuoso simulator. Everything are ok before doing the impedance matching. I observable the input an output impedance by applying the sp analysis and plot the impedance waveform for input and output port. After impedance matching is done (either input or output port). I found the real part of the impedance at another port will become negative. I understand that the negative impedance will only occur when we deal with the oscillator circuit. What I want to ask are:
1. Is this situation caused by the gate-drain capacitance which act like a feed back loop at the high frequency operation?
2. Can I just ignored it and what should I do in order to continue the matching process( just ignored the negative sign at the real part?) If this problem could not be neglected, what should I do to solve this problem?
Thank you!
Information:
loaded quality factor, QL = 5; operating frequency = 2.4 GHz; supply voltage = 1.2V;CMOS technology = 0.13 um; substrate width = 500 um. L1 = 200 nH; C1 = 290.85fF; L2 = 16.5786 nH; C2 = 352.456 fF.
1. Is this situation caused by the gate-drain capacitance which act like a feed back loop at the high frequency operation?
2. Can I just ignored it and what should I do in order to continue the matching process( just ignored the negative sign at the real part?) If this problem could not be neglected, what should I do to solve this problem?
Thank you!
Information:
loaded quality factor, QL = 5; operating frequency = 2.4 GHz; supply voltage = 1.2V;CMOS technology = 0.13 um; substrate width = 500 um. L1 = 200 nH; C1 = 290.85fF; L2 = 16.5786 nH; C2 = 352.456 fF.
