Post -synthesis simulation

[kalyansrinivas]

post synthesis simulation test bench

Hi friends
I am trying to run my post synthesis simulation using Modelsim , Xilinx has generated the .vhd file along with .nlf (net list file) when i run the post synthesis .When i simulate using M-sim i see the outputs as unknown value from only the modules having coregenerator instances .So i added the (.edn, .ngc) of coregenerator to my project directory along with synthesis output files(.vhd,.nlf) .But even i find unknown results from the core instances

please help

 

[srinivasan_b1]

xilinx ise + coregen + post-synthesis simulation

Hi Kalyan,

Before you do Post Synthesis Simulation you should decide why you need to do that. Post Synthesis simulation will not give actual results as you expect on your Actual Hardware Board. So you should do Post Place-Route Simulation.

You can do that only if you know I/O constraints, Board constraints etc. So what ever simulation you do Modelsim is good. Modelsim does not know you nlf,ngc,edn etc. It knows only HDL and Test Bench files.

So first you give your Physical constraints in UCF, do Placement and Routing. Then Generate Post Place-Route Model from ISE. It will be a VHDL or VerilogHDL file (as you require). Then write your test bench either by yourself or by waveform editor. While doing that your stimulis should be such a way that you check the performace in worst case scenarios and whether the given constraints are met or not.

Then add this Post place and route model with test bench to Modelsim project. Also add the Unisim, Vsim libraries whose HDL sources you can find in you ISE Installation folder. Choose those libraries for the Device for which you placed and routed. Compile those libraries first in Modelsim and then Compile the whole project. Your Test bench will be the top level module. Now you can run it and get the complete simulation result.

Check the ooutput waveforms for the required constraints. Once its successfull, You learnt FPGA design thouroughly. Thanks. Any doubt you can contact me.Even in Post Synthesis Simulation you should add those libraries.

srinivasan_b1@yahoo.co.in



with regards,
Srinivasan

 

[kalyansrinivas]

post synthesis simulation in ise

Hi srinivasan
Thank you i just done post synthesis simulation as a pre verification without timing but the problem i faced it is that when i run till generate post synthesis simulation model it doesnt integrate the core-genarator output files .I found the output to be of unknown from core-gen instantiation modules when i run the post synthesis simulation .so i runned the design till translate phase and generated post -translate simulation model .The translate phase only integrated the coregen output modules to the design .So than i got the results correctly. I am not verifying the timing here i want just verify the functionality

So what i understood is that i should run till translate phase when i have coregen instantations in my design for checking the functionality

 

[xtcx]

post-synthesis versus post place and route

Post Synthesis simulation will not give actual results as you expect on your Actual Hardware Board. So you should do Post Place-Route Simulation.

Hi Srinivas,I use to do Post synthesis in M-sim.So much of y design have seemed to be right at first but failed in realhardware.I Never have used Post Place-Route sim using M-sim. Could you explain me how to do it in steps or is there any link that describes it?...Your help is much appreciated!....Thanks yo

 

[kalyansrinivas]

testbench for post synthesis simulation

Hi xtcx
In Xilinx ise run generate - post place n route simulation model This generates the .v,.vhd files along with the .sdf file and .nlf file . Now run in m-sim by adding .sdf file to the design

 

[xtcx]

how to use post synthesis simulation model

Oh Thanks a lot Kalyansrinivas....I'll see for it and ask for any doubts!....Thanks

 

[xtcx]

post synthesis is simulation

So first you give your Physical constraints in UCF, do Placement and Routing. Then Generate Post Place-Route Model from ISE. It will be a VHDL or VerilogHDL file (as you require). Then write your test bench either by yourself or by waveform editor. While doing that your stimulis should be such a way that you check the performace in worst case scenarios and whether the given constraints are met or not.

Then add this Post place and route model with test bench to Modelsim project. Also add the Unisim, Vsim libraries whose HDL sources you can find in you ISE Installation folder. Choose those libraries for the Device for which you placed and routed. Compile those libraries first in Modelsim and then Compile the whole project. Your Test bench will be the top level module. Now you can run it and get the complete simulation result

Hi friends!, I don't understand why you need to create a testbench and then add it to your model-sim project...?..I get a vhd file in a folder called "netgen" after I do "Generate POST PLACE AND ROUTE SIMULATION MODEL" in IMPLEMENTATION. What should I do with this file?...Can I simply run modelsim by adding this vhd file alone to get the complete simulation results?...Please if anybody could explain, it'd be a big help!...Thanks