[SOLVED] post Synthesis simulation problems

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Tychus

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Hi all,

I'm having problem with my design (fibonacci generator) i've been trying to fix this for the past few days in vain. I'm using Cadence RTL and Modelsim for the simulation. The netlist generated from this give no warnings or errors but still doesn't simulate right anyone can give some pointers ?

Code VHDL - [expand]
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity fibonacci is
 port(
      clk, rst : in std_logic;
      limit : in std_logic_vector(9 downto 0);
      fibo_series: out std_logic_vector(9 downto 0)
      );
end fibonacci;
 
architecture fibonacci of fibonacci is
 signal a,b,c : std_logic_vector(9 downto 0);
begin
 process(clk,rst)
 begin
  if(rst = '1') then
   b <= std_logic_vector(to_unsigned(1, limit'length));
   c <= std_logic_vector(to_unsigned(0, limit'length));
  elsif(clk'event and clk='1') then
   if(c = limit) then
       b <= std_logic_vector(to_unsigned(1, limit'length));
       c <= std_logic_vector(to_unsigned(0, limit'length));
   else 
       c<=b;
       b<=a;
   end if;
  end if;
 end process;
 a <= std_logic_vector(unsigned(b) + unsigned(c));
 fibo_series <= c;
end fibonacci;
 

Firstly, does the RTL simulation look OK?

Then, how does the netlist simulation differ from the RTL simulation?
 

After synthesizing the design i get a verilog netlist file which i simulate in modelsim; the simulation does not give any output.
 

That doesn't address the first question: does the RTL simulation look okay?

What is the output netlist simulation showing? Do you have a testbench that you use for both the RTL and netlist simulation, or are they different?
 

There's no problem with the design itself, most likely a wrong testbench.
 

I don't know what an RTL simulation means i was given instructions to synthesize with cadence and simulate with modelsim both before and after synthesis. this is the testbench i'm using testing the vhdl design generates correct output but simulating verilog netlist doesn't.

Code: 
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity testbench is
end testbench;

ARCHITECTURE behavioral of testbench is
   --Input and Output definitions.
   signal clk : std_logic := '0';
   signal rst : std_logic := '1';
   signal limit : std_logic_vector(9 downto 0);
   signal fibo_series : std_logic_vector(9 downto 0);
   -- Clock period definitions
   constant clk_period : time := 2 ns;
BEGIN
   -- Instantiate the Unit Under Test (UUT)
   uut: entity work.fibonacci PORT MAP (
          clk => clk,
          rst => rst,
          limit => limit,
          fibo_series => fibo_series
        );
   -- Clock process definitions
   clk_process :process
   begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
   end process;
   
   testing: process
   begin
    rst <= '0';
    limit <= std_logic_vector(to_unsigned(233, limit'length));
    wait for clk_period;
   end process;
END;

sorry if i don't answer correctly this assignment was dumped on us without any instructions or guides i'm a total noob when it comes to vhdl and what goes with it.
 

Once again what is the OUTPUT of the simulation showing in Modelsim when the netlist simulation is run.

Why do I even bother asking the OP anything when they ignore my questions...why do I even bother trying to help :bang:
 

like i said the simulation does not generate ANYTHING output does not carry any value. i believe i answered that in the first reply
 

What the simulation just sits a 0 ns forever, the output wave window is blank, the output is some value that you don't like? what is ANYTHING mean (well it's a meaningless word in this case).

- - - Updated - - -

Just post a screen capture of what you see in your wave window in modelsim.
 

Ok here's what happens simulating the netlist generates clock signal, the limit signal also carries the correct value. the output remains red even if i simulate for 1000ns. XXXXXXXX i attached an image of vhdl simulation (the one that works) the last signal is what i'm having problems with. hope this explains it because i don't know hos i can explain it more.




EDIT: i don't have a snapshot of the wrong netlist simulation.
 
Last edited:

Okay now you've actually supplied useful information, but didn't show the broken simulation results. sigh...

If you have an output of X on the fibo_series output it's because you have a problem with uninitialized signals, which you never correctly initialize in your testbench using the rst signal. So I'm not surprised you have X on the fibo_series output.

- - - Updated - - -

Edit,

FYI, having an X on an output is not the same as no output, it IS an output just a bad output.
 

I see at least two problems, each of it might cause failure in gate level simulation.

- zero duration of reset pulse
- 500 MHz clock is probably too fast for the simulated hardware
 

FvM said:
- 500 MHz clock is probably too fast for the simulated hardware
Click to expand...

FvM this is for an ASIC, I'd be really surprised if this frequency wasn't achievable in today's technology or even yesterdays technology.
 

fix your reset, then we will see if there is any real error
 


Please post another VHDL design waveform with the same signal and time frame with Netlist design.
And do simple steps below and get back to us:
1/ Please make sure VHDL simulation is correct.
2/ Compare VHDL and Netlist simulation waveforms.
3/ If (2) does give a result, post the result of (2) when you can not find the answer by yourself.
 

Here is the waveform from netlist simulation as you can see it does not generate the fibonacci series like the post synthesis simulation.



would you like me to include logs from cadence, ads-ee and thisisnotsam suggested i fix my rst in testbench i have no idea what to fix and how i initialized clock and reset in the testbench any guides on how i can do that ?
 

If this can be of any help cadence throws these warnings after the elaborate command:

 

The cadence report indicates your clock constraints are using the wrong edges, can't say if it is the wrong cells being used, messed up constraints, or what from this end.

Add a delay before the rst <= '0'; line in testing process e.g. wait 100 ns;

- - - Updated - - -

Edit clock and reset are already initialize in the signal declaration in your testbench. What wasn't initialized was the signals in you fibo.. code, which were end up propagating x's at the output.

FYI using initializing declarations in an ASIC will not work so don't bother adding them for simulation. If you must then check both high and low initial values on every FF that is initialized in the signal declaration.
 
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    Tychus

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you have to stop clicking buttons and think about what you are doing. we have told you that the reset is the problem. the tool is clearly telling you too, that red line is there for a reason! fix that before you keep going.

and for the sake of all involved parties, stop saying cadence is throwing warnings. cadence is a company, not a tool. the warnings are from rtl compiler. if you want help with synthesis you have to post the entire sequence of commands you are using. you might have picked the wrong library, or they might be benign warning messages. hard to tell.
 

ads-ee suggestion fixed the issue. I'm not just clicking buttons this is not what i do for a living nor what i want to do this was dumped on me with a set of instructions that serve nothing the whole problem is the red line i do not know what it is or why it is there that is why I'm asking you guys. for cadence being the company not the compiler i know cadence is a company but that's what everybody calls the thing, in fact in the instructions it says "use cadence ... ". please try not to be arrogant and condescending if you want to help do it nicely or don't.

The thread is marked solved
 
Last edited:

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