[SOLVED] post synthesis problem in ram1024x64

Hi edaboard,
In my project I am using dual port block rams... Functional simulation is correct but for post synthesis simulation my output results are wrong.. I saw nets and reg (both input and outputs using "KEEP" attribute) input data and address lines are going correct, but while reading I got some random output data for the given address lines (in output in between zeros are comming). please help me I stuck here..(I unable to implement on board because of this)

I am posting my code and wave forms..

module ram1024x64( datain1_re,
datain1_im,
datain2_re,
datain2_im,
valid_wr,
valid_rd,
clock,
dataout1,
dataout2,
load_in,
addr1_wr0,
addr1_wr,
addr2_wr,
addr2_rd,
addr1_rd,
valid_wr0
);

/* Parameter declaration */
parameter N = 10;
parameter width = 32;

/* Input declarations */
input valid_wr;
input valid_wr0;
input valid_rd;
input clock;
input load_in;
input [width-1:0]datain1_re;
input [width-1:0]datain1_im;
input [width-1:0]datain2_re;
input [width-1:0]datain2_im;
input [N-1:0]addr1_rd;
input [N-1:0]addr2_rd;
input [N-1:0]addr1_wr;
input [N-1:0]addr2_wr;
input [N-1:0]addr1_wr0;


/* Output declarations */
output reg[(2*width)-1:0] dataout1;
output reg[(2*width)-1:0] dataout2;

/* Internal register declaration */
(* KEEP = "TRUE" *)reg [(2*width)-1:0]ram[02**N)-1];
(* KEEP = "TRUE" *) wire [N-1:0]addr1_wr_d;

/* Internal wire declaration */
(* KEEP = "TRUE" *)wire [(2*width)-1:0]datain1;
(* KEEP = "TRUE" *)wire [(2*width)-1:0]datain2;

assign datain1 = {datain1_re,datain1_im};
assign datain2 = {datain2_re,datain2_im};


assign addr1_wr_d = valid_wr0 ? addr1_wr0 : addr1_wr;
always @(posedge clock)
begin
if(load_in & valid_wr0)
begin
ram[addr1_wr_d] <= datain1;
end
else
begin
if(valid_wr0 & !load_in)
begin
ram[addr1_wr_d] <= 0;
end
else
if(valid_wr)
begin
ram[addr1_wr_d] <= datain1;
ram[addr2_wr] <= datain2;
end
end
end
always @(posedge clock)
begin
if(valid_rd)
begin
dataout1 <= ram[addr1_rd];
dataout2 <= ram[addr2_rd];
end
end

endmodule

- - - Updated - - -

I am using xilinx ise 14.2 and modelsim 10.3g.. can we see ram (memory) in the output wave forms while post synthesis simulation.. if yes please suggest

found solution .... while loading of data .. I am using only one address port for writing addr1_wr_d, by default addr2_wr_rd having some address.. when addr1_wr_rd approaches to address of addr2_wr_rd memory collision happend .