modelsim sdfmax
#******************************************
# For Modeltech Simulator.
#******************************************
#VHDL
vlib work (create working library)
vlib target (create technology library)
vcom tech.vhd -work target (compiling technology library)
vcom -explicit netlist.vhd (compiling synopsys vhdl output)
vcom -explicit test_benches.vhd (compiling your test benches)
vsim -t ps -sdfmin /UUT=netilst.sdf test_benches (vsim with time=ps timing min (sdfmin/sdftyp/sdfmax) backannotation file= netlist.sdf (file writed by synopsys with command write_sdf (I'm not sure)) test_benches=architecture name of your test benches)
#Verilog
vlog -explicit netlist.v
vlog -explicit test_fixture.v
vsim -t ps -sdfmin /UUT=netilst.sdf test_fixture