dipin
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hi,
i had a problem in my design. when i do post route simulation its output coming early than expected.
in this waveform output must come in the next rising edge of the clock (190,000 ps). but the output is coming before that !!!! how it is possible???
if the output is delayed means its ok. but the output coming early.
how can i justify this??
this is my test bench
and here is my design
if anybody know please help.
thanks & regards
i had a problem in my design. when i do post route simulation its output coming early than expected.
in this waveform output must come in the next rising edge of the clock (190,000 ps). but the output is coming before that !!!! how it is possible???
if the output is delayed means its ok. but the output coming early.
how can i justify this??
this is my test bench
Code:
module sqrt_test();
reg [31:0]in_data;
reg clk;
reg reset;
reg [31:0]count;
wire [16:0]out_data;
wire [17:0]remainder;
//wire [67:0]temp_in_data1;
//wire [63:0]xtemp_in_data_1;
sqrt U1(
.in_data(in_data),
.clk(clk),
.reset(reset),
.out_data(out_data),
.remainder(remainder)
// .temp_in_data1(temp_in_data1),
// .xtemp_in_data_1(xtemp_in_data_1)
);
initial begin
clk =1;
reset =1'b1;
in_data =32'd0;
count = 0;
repeat(10) @(negedge clk);
reset=1'b0;
count = 40001;
end
always@(posedge clk) begin
if(!reset) begin
in_data = count;
count = count+1;
end
end
always begin
#5 clk <=~clk;
end
endmoduleand here is my design
Code:
module sqrt(
in_data,
clk,
reset,
out_data,
remainder
);
parameter IN_WIDTH = 31; // INPUT WIDTH
parameter OUT_WIDTH = IN_WIDTH >> 1;
parameter IN_CAL = IN_WIDTH >> 2;
parameter N = 4*(IN_CAL+1);
parameter Q = N >> 1;
input [N-1:0] in_data;
input clk;
input reset;
output [Q:0] out_data;
output [Q+1:0] remainder;
reg [Q:0] out_data;
reg [Q+1:0] remainder;
reg [Q:0] xa_out_data [12:0];
reg [Q:0] temp_out_data;
reg [2*N+3:0] temp_in_data[13:1];
reg [2*N-1:0] xtemp_in_data_1;
reg [2*N-1:0] xtemp_in_data_2;
reg [2*N-1:0] xtemp_in_data_3;
reg [2*N-1:0] xtemp_in_data_4;
reg [2*N-1:0] xtemp_in_data_5;
reg [2*N-1:0] xtemp_in_data_6;
reg [2*N-1:0] xtemp_in_data_7;
reg [2*N-1:0] xtemp_in_data_8;
reg [2*N-1:0] xtemp_in_data_9;
reg [2*N-1:0] xtemp_in_data_10;
reg [2*N-1:0] xtemp_in_data_11;
reg [2*N-1:0] xtemp_in_data_12;
reg [N-1:0] temp_sub_result_1;
reg [N-1:0] temp_sub_result_2;
reg [N-1:0] temp_sub_result_3;
reg [N-1:0] temp_sub_result_4;
reg [N-1:0] temp_sub_result_5;
reg [N-1:0] temp_sub_result_6;
reg [N-1:0] temp_sub_result_7;
reg [N-1:0] temp_sub_result_8;
reg [N-1:0] temp_sub_result_9;
reg [N-1:0] temp_sub_result_10;
reg [N-1:0] temp_sub_result_11;
reg [N-1:0] temp_sub_result_12;
always @(posedge clk)begin
if(reset) begin
temp_in_data[1] <= 0;
temp_in_data[2] <= 0;
temp_in_data[3] <= 0;
temp_in_data[4] <= 0;
temp_in_data[5] <= 0;
temp_in_data[6] <= 0;
temp_in_data[7] <= 0;
temp_in_data[8] <= 0;
temp_in_data[9] <= 0;
temp_in_data[10] <= 0;
temp_in_data[11] <= 0;
temp_in_data[12] <= 0;
temp_in_data[13] <= 0;
xtemp_in_data_1 <= 0;
xtemp_in_data_2 <= 0;
xtemp_in_data_3 <= 0;
xtemp_in_data_4 <= 0;
xtemp_in_data_5 <= 0;
xtemp_in_data_6 <= 0;
xtemp_in_data_7 <= 0;
xtemp_in_data_8 <= 0;
xtemp_in_data_9 <= 0;
xtemp_in_data_10<= 0;
xtemp_in_data_11<= 0;
xtemp_in_data_12<= 0;
temp_sub_result_1 <= 1;
temp_sub_result_2 <= 1;
temp_sub_result_3 <= 1;
temp_sub_result_4 <= 1;
temp_sub_result_5 <= 1;
temp_sub_result_6 <= 1;
temp_sub_result_7 <= 1;
temp_sub_result_8 <= 1;
temp_sub_result_9 <= 1;
temp_sub_result_10<= 1;
temp_sub_result_11<= 1;
temp_sub_result_12<= 1;
xa_out_data[0] <= 0;
xa_out_data[1] <= 0;
xa_out_data[2] <= 0;
xa_out_data[3] <= 0;
xa_out_data[4] <= 0;
xa_out_data[5] <= 0;
xa_out_data[6] <= 0;
xa_out_data[7] <= 0;
xa_out_data[8] <= 0;
xa_out_data[9] <= 0;
xa_out_data[10] <= 0;
xa_out_data[11] <= 0;
xa_out_data[12] <= 0;
remainder <= 0;
out_data <= 0;
end else begin
temp_in_data[1][N+1:2] <= in_data[N-1:0];
xtemp_in_data_1[N+3:4] <= in_data[N-1:0];
temp_sub_result_1 <= 1;
xa_out_data[0] <= 0;
out_data <= xa_out_data[IN_CAL+1];
remainder <= temp_in_data[IN_CAL+2][N+3+Q:N+2];
if(condition)begin
if(condition) begin
...............
end else begin
.............
end
end else begin
if(condition) begin
................
end else begin
................
end
end
. .
...........
.........
.........thanks & regards
Last edited: