Post-layout simulation

Dar89 said:

Hello, this is my first post, I hope this is the correct section . I've designed a D flip-flop and I've realized the layout, then, with starXCT, i've extracted parasitic and maked the post layout simulation. I have to design a very speed flip-flop to use it in a full custom design, so I'm interested to delay (time to clock and setup time). The effect of parasitic ( extracted with a RCmax methodology) is the following:
TcqLH=45.09 ps (schematic)->53 ps (post-layout simulation)
TcqHL=45.16 ps (schematic)->67.54 ps (post-layout simulation)
I don't have experience in this situations, but for me, the delay in the case of TcqHL is too high, respect to the schematic simulation. So i've indentified the capacitances responsible of that and i've incremented the W of some mosfet in the layout (without moving any interconnect), obtaining the following timing:
TcqLH=43.21 ps (schematic)->52.38 ps (post-layout simulation)
TcqHL=40.24 ps (schematic)->57.11 ps (post-layout simulation)
The percentage of parasitic on delay in the two cases is the same, but now i go a little fast. Is this degradation of timing caused by interconnect acceptable?

Thanks

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