Hi terry8,
The verilog which modelise the flop contains some time check (hold/setup).
The sdf back attonate the verilog to indicate what are the margins and delay...
During your simulation post-layout with timing, the simulator will check that all this time check are respected, like hold time on D pin versus CLK pin.
If your design is timing clean, and the D pin is driven by an other memory element (flop or memories), the hold must not violated. A violation means, wrong timing constraint that mask the hold checks.
If the D pin is driven by an asynchronous signal, that is not "controllable" when it is asserted & de-asserted, the timing check versus the CLK pin must be ignore because, the place and route tool does not know the timing relation.
is it more clear?