terry8
Newbie level 3
i meet a big problem
i finish the all of steps from DC & ICC,
there is no timing violation in DC & ICC
and also the pre layout simulation & DRC & LVS is correct.
when i do the post layout simulation in ncverilog
some error like this
"tsmc18.v", 21081: Timing violation in testtop.u1.core.y_reg_2_
$setuphold<hold>( posedge CK &&& (SandRandSEb == 1):93500, posedge D:93500, 1.00 : 100, 1.00 : 100 );
what it means? really confuse me long time!!
who can help me? thx
i finish the all of steps from DC & ICC,
there is no timing violation in DC & ICC
and also the pre layout simulation & DRC & LVS is correct.
when i do the post layout simulation in ncverilog
some error like this
"tsmc18.v", 21081: Timing violation in testtop.u1.core.y_reg_2_
$setuphold<hold>( posedge CK &&& (SandRandSEb == 1):93500, posedge D:93500, 1.00 : 100, 1.00 : 100 );
what it means? really confuse me long time!!
who can help me? thx