Post-Layout simulation results not matching schematic simulations

I am replicating an IEEE paper using Low-Power split-path data-driven dynamic logic. Since they are not standard logic blocks I was not able to synthesize it from RTL so I did fully custom schematic and layout by hand. The design is a 16x16 bit multiplier, and the layout passes DRC/LVS without any warnings or errors.

I have ran about 35 random test cases for the schematic netlist and they all pass. The problem is when I run the netlist with the PEX data. Of the 10 cases I ran for the post-layout simulation, 6 of them passed and 4 of them failed. The 4 failing test cases do not seem to be related i.e different bits are returning bad data on each of the tests. I have already tried increasing the evaluation time (giving it 4x longer to evaluate than it actually takes), and they still do not pass.

What I am thinking about next is to try the following:

- Adding extra nets/pins to large fan-out nets to decrease the parasitic effects
- Increasing the voltage of the inputs
- Adding buffers to outputs to sub-block outputs to re-assert the logic value on high fan-out nets

I was wondering if I am missing something obvious since I have been looking at this too long? Or should I go ahead with what I listed above? Any input would be great! Thanks!

did you run your simulations without pex data, to have only the functionnality and no cross-talk?
adding power-up time and delay to have design stabilize and check the result "later".

I have run the same tests from my schematic netlist and they have all passed, and LVS passes with no errors. I assume since LVS passed I just have to put it in with the pex results.

Are you talking about extracting the netlist from the layout and running without the pex data?

without pex data