Wawan66
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cadence calibre post-layout simulation
Hi,
The story begins here : I'd like to simulate an inverter layout. The design has been created with Cadence Virtuoso. I've checked it with Calibre DRC. The technology used is ST CMOS090. In order to validate this final step, I need to run a post-layout simulation (PLS). I use the PLS kit installed with the design kit. When I click on Run PLS, the PLS init step failed. Here is the related log file :
Can someone help me please?
Thank you very much
Hi,
The story begins here : I'd like to simulate an inverter layout. The design has been created with Cadence Virtuoso. I've checked it with Calibre DRC. The technology used is ST CMOS090. In order to validate this final step, I need to run a post-layout simulation (PLS). I use the PLS kit installed with the design kit. When I click on Run PLS, the PLS init step failed. Here is the related log file :
Can someone help me please?
Thank you very much