Post-layout simulation kit

[Wawan66]

cadence calibre post-layout simulation

Hi,

The story begins here : I'd like to simulate an inverter layout. The design has been created with Cadence Virtuoso. I've checked it with Calibre DRC. The technology used is ST CMOS090. In order to validate this final step, I need to run a post-layout simulation (PLS). I use the PLS kit installed with the design kit. When I click on Run PLS, the PLS init step failed. Here is the related log file :

#############
# PLS 1.2 #
#############
### Info: Use default staRCXT option configuration file /usr/local/DesignKit/cmos090_40b1/PLSKit_1.2/interface/PLScommands (PLSinit).
### Info: File /usr/local/DesignKit/cmos090_40b1/DK_cmos090gp_7M2T_50A_4.0b1/MODULES/DKcmos090gp_7M2T_PLS/MODULES/DKcmos090gp_7M2T_starrcxt/cmos090gp_7M2T.calibrestarrcxtGuiswitchdef copied to file /users/archi/grace/Cadence/plsimulation/test_90nm-inverter-schematic/test_90nm-inverter-layout/phase2/pls1/initDir/cmos090gp_7M2T.calibrestarrcxtGuiswitchdef. (dkCustCalibreIFileCopy).
### Fatal Error -Exiting-: Key 'calibreGuirunsetlvs' was not found in product (table) '/usr/local/DesignKit/cmos090_40b1/DK_cmos090gp_7M2T_50A_4.0b1' (piGetInfo) (PLSinit).

Can someone help me please?

Thank you very much

 

[tsinghua]

It seems that the problem resulted from the Calibre GUI LVS configuration with the PDK. Please contact with the foundry to get cad support.

 

[sat]

You cannot run PLS on a layout - you need to have the extracted netlist to run PLS.
Before going to post layout simulation - you need to extract designed devices (Calibre LVS) and parasitics (StarRCXT) as well. I believe, you need to follow LVS methodologies and then parasitic extraction etc..