post layout simulation debugging on the parasitic extraction (PEX) results

[allennlowaton]

I had finished doing the chip layout of the LED driver IC. The post layout simulation of each block performs well. Moreover, the whole chip layout passed the DRC as well as the LVS. But, the post layout simulation fails. I was advised to debug it from the parasitic extraction results (PEX). The PEX might be wrong. I'm using Cadence Virtuoso and HSpice.
The mere thought of dipping myself into those weird multitude nodes and meticulously sorting them shatters me more. Do you think it's sensible for me to do that? Please share your experiences on this. I'm kinda frustrated already.

 

[timof]

Do you have an idea on what kind of parasitic effects might be affecting your design?
(capacitance, resistance, Rdson increase due to source/drain metallization, matching several channels resistances or currents, etc.)?

Or are you trying to use parasitic extraction as a black box, hoping that it will magically capture and predict some effects critical for your designs?

Here is a couple of useful links, relevant for LED drivers:

1. a paper on thermal runaway in multiple LED strings due to manufacturing LED mismatch:

**broken link removed**

2. a simulation approach for power device interconnects analysis and optimization:

https://www.siliconfrontline.com/fi...d_National_Semiconductor_ISPSD-2010_LV-P4.pdf

 

[allennlowaton]

I suspect it's the parasitic resistance. In a certain block, I used the C+CC extraction type instead of the R+C+CC option. The results went well. But when I integrated the whole chip, even though I got a clean LVS. There are some block (voltage bandgap, in my case) fail.
Apparently, I consider the PEX file I used for the post layout simulation as a black box. I didn't know where to begin in debugging my post layout.

 

[Braski]

can you debug only few blocks together instead of the whole chip or only single blocks? maybe in this way you can find the problem