Possible latch up in fabricated chip

[Alchemist_]

Dear all,

I designed a mixed signal asic with tsmc 65 nm process for research purposes. A lab expert suggested me to avoid the pad ring for speeding up the gds delivery. Now I'm trying to measure the fabricated chip and I'm experiencing a very strange behavior from the circuit. In short, it behaves unexpectedly with output pins to fixed voltages. More specifically, some digital outputs show a voltage between ground and supply voltage. Moreover, some samples show a very high current consumption in the order of tenths of milli amps.

Could the absence of pad ring cause a latch up phenomenon on my circuit?

Thanks for support.

 

[dick_freebird]

Unlikely a direct cause, but potentially allowing "pin" voltages
to go someplace that's capable of provoking latchup if you force
that. Pad cells for digital signals at least tend to limit the travel.
I
If outputs are at vdd/2, are you sure it's not oscillating?

Latchup should be recoverable by power cycling and its
signature would be elevated idd.

Now if you "rolled your own" I/Os, especially output drivers, you
might have ignored some latchup suppression features that are
prescribed for I/Os. If you create cells without the appropriate
recognition features, or use "core" devices instead of "I/O" ones,
the DRC may let you get away with it.

 

[Alchemist_]

Hi dick_freebird and thanks for your reply.

Pad cells for digital signals at least tend to limit the travel.
I
If outputs are at vdd/2, are you sure it's not oscillating?

Please could you explain what do you mean by "limit the travel"?

Digital outputs seem to assume a fixed random voltage (e.g., 100 mV, 1 V, etc) and they do not oscillate. That's really strange since they are outputs of basic CMOS inverters (custom cells, not standard cells).

Regarding analog outputs, their behavior vary depending on tested chip. On some they are at fixed voltage which do not makes any sense. On others, they resemble the simulated behavior but with wrong signal amplitude. It seems like MOSFETs with direct connection pad-gate have been damaged due to overcurrents. Is this possible with latch up?

Latchup should be recoverable by power cycling and its
signature would be elevated idd.

So, from this I understand that latchup is a reversible (non destructive) process. I confirm an high current consumption from vdd.

Now if you "rolled your own" I/Os, especially output drivers, you
might have ignored some latchup suppression features that are
prescribed for I/Os. If you create cells without the appropriate
recognition features, or use "core" devices instead of "I/O" ones,
the DRC may let you get away with it.

How can I reproduce the latch up problem in simulation environment?

 

[dick_freebird]

Simulator models tend to only be the explicit device
unless there is a really sophisticated layout extraction
capable of representing all the buried BJTs in the
neighborhood. As an academic exercise I have seen
this. As a real, usable CAD function, no way.

However what I do suggest is to look at any failing
("damaged") output's layout to see that (1) tap rules
are not violated and (b) that any pad connected device
employs the prescribed I/O guardring rules.

Be sure that no input is allowed to "float" to an unknown
voltage (or a voltage where the outcome is "X"). This can
also product the elevated supply current signature and
possibly corrupt signal chain all the way to an output.

Latchup is reversible, until it isn't. You can survive
"micro-latch" (single transistor or pair, that pulls less
current than the interconnect can handle long term)
but as you approach chip scale (like lighting up a
very large NWell made contiguous to hold all the
PMOS of an I/O ring) could fry traces or even bond
wires. Depending on chio design you could see a
"staircase" of local latchups, one SCR at a time. See
this at single event effects testing a lot, random ion
strike location triggering one at a time until "She canna
take any more, Captain!"

Pin induced electrical latchup is what the design rules
are meant to prevent. An input (or output) whose N+/Pepi
or P+/NWell junction goes forward biased (i.e. travels
outside the supply rails to which Pepi or NWell is tied)
injects base current to "something". If that's the shunt R
delivered by tap proximity and guardring enclosure, it
can be kept benign. But that R is finite and layout defined.
Site by site, transistor by transistor, don't miss one.

"Hot" NWells are their own special threat. Buried in the core
and escaping basic DRC rules, this presents a deep junction
which could be forward biased by circuit topology and
operation (normal or abnormal).

If you proceed in an orderly way with capturing power-up
pin activity, you might be able to deduce what has provoked
the latchup. Monitor supply current, set an intial "maximally
benign, maximally known" condition, then start working your
way toward normal operation one signal or signal-group at
a time, one load at a time, see where stuff goes nuts, follow
the thread.

 

[Alchemist_]

dick_freebird, thank you for your detailed reply. That is actually the only help I got.

However what I do suggest is to look at any failing
("damaged") output's layout to see that (1) tap rules
are not violated and (b) that any pad connected device
employs the prescribed I/O guardring rules.

The layout is DRC-clean. This was also confirmed by our silicon provider. Is it possible for a fabricated chip without DRC problems to exhibit latchup issues?

Please keep in mind that, as I specified in the first post, no technology's IO cells have been used. The input pads are directly connected to core gates (analog/digital) and the output devices are directly connected to pads.

Pin induced electrical latchup is what the design rules
are meant to prevent. An input (or output) whose N+/Pepi
or P+/NWell junction goes forward biased (i.e. travels
outside the supply rails to which Pepi or NWell is tied)
injects base current to "something". If that's the shunt R
delivered by tap proximity and guardring enclosure, it
can be kept benign. But that R is finite and layout defined.
Site by site, transistor by transistor, don't miss one.

Are you referring to non-zero gate currents? That rang a bell, so I would like to know more on "pin induced electrical latchup".

Regarding your advice, this is a good practical one. I will try to figure out pin-by-pin what's happening.

Now the billion $ question: based on your experience, assuming latchup is the only real cause of malfunction (circuit simulation is ok), does adding a proper padring with I/O cells guarantee I won't fail the next tape-out?

Again thanks for your help.

 

[dick_freebird]

There are other threats which can damage inputs or outputs.

I have worked in some SOI technologies where design choices
(for RF) dictated leaving off all ESD protection. There, "3.3V" FETs
showed a 10V HBM ESD damage threshold. Yes. 10V. No "k".

You might (if so equipped) pull some I-V curves on a normal
virgin chip powered up normally, and compare to your damaged
samples. G-D conductive "shorts" (or resistive filaments through
oxides) can cause all sorts of behavior-shifts (short, leak, hot carrier
induced VT / leakage floor shifts). If short on gear, try a DMM at a
couple of forced voltages and poor-boy it.

Hopefully you are equipped at least with good handling-ESD wrist
strap, chair chains and bench all resistively grounded (1M) and on
a ESD-safe flooring. 1V-ish core devices are not built to take a punch.
Not even a slap-fight.

 

[Alchemist_]

Thanks for the suggestions.

A small update: I showed the measurement setup to an expert designer. He was pretty confident that the chip malfunction, along with the high power consumption, is due to oscillations of internal nodes. The reasons could be related to wrong layout choices such as a low bypass capacitance on Vdd. Moreover, he said that logic gates directly connected to pads (without IO cells) can be easily broken due to ESD. He excluded latchup issues since the currents in my circuit are relatively low (from hundreds of nA to hundreds of uA).

What is you opinion on this?

I'm trying to reproduce the malfunction in simulation environment by modeling bonding wires, pads and PCB tracks but the circuits works properly. I'm also trying a PEX simulation and the circuit continues to work properly.

Do you suggest any other methods for testing the circuit in simulation?

I consider this as an important step towards success of the next tape out.

Thanks for help.

 

[D.A.(Tony)Stewart]

How do you control/simulate/measure Igs leakage with a shrinking gate path?

How do you control/prevent/simulate or measure external E-field latchup with parasitic EM crosstalk from G to D?

Does Zo impedance match your expectation when back driving outputs?

Have you tried back-driving current limited AC testing on outputs to check for [pF] modulation vs expected PN diode effects and characteristics of ESD damage with rising C(V) due to reduced junction width?

I used this method for LEDs to prove ESD was an integrator factory handling issue and similar to the Huntron test method and identified the many risks in a list then resolved the problem with an integrated ESD diode in the LED. But here speed was not an issue just robust components. I recall the Tek Diff probes in the early 80's had their FET inputs frequently replaces by our lab tech. You could just raise an arm and exceed the 25V breakdown potential in E-Field unless you were grounded to the probe ring at all times until the shorting tip was installed. I could just raise a leg and exceed 200V by just changing my body capacitance to ground. V=Q/C