Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

possible issues to be considered while designing a capacitor in cadence/spice/ads

Status
Not open for further replies.
T

the_falcon

Member level 4
Member level 4
Joined
May 28, 2010
Messages
72
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Toronto
Visit site
Activity points
1,811
hi all,
i am interested to know the possible issues to be considered while designing a capacitor in cadence/spice/ads.

though it sounds simple, i would like to get the public opinions and suggestions so that everyone can get benefit out of it

falcon
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top