Guru59
Full Member level 4
Hi all,
Below is the verilog code for posedge and negedge flipflops using mux.
I have also attached the pictorial representation of the circuit.
Verilog code :
module mux_ff(
clk,
in,
out_pos,
out_neg
);
input clk;
input in;
output out_pos;
output out_neg;
wire clk;
wire in;
reg out_pos;
reg out_neg;
reg pos_reg,neg_reg;
always @ (clk or in)
begin
pos_reg = ~ clk ? in : pos_reg ;
out_pos = clk ? pos_reg : out_pos ;
end
always @ (clk or in)
begin
neg_reg = clk ? in : neg_reg ;
out_neg = ~ clk ? neg_reg : out_neg ;
end
endmodule
correct me if i am wrong.....thanks
Below is the verilog code for posedge and negedge flipflops using mux.
I have also attached the pictorial representation of the circuit.
Verilog code :
module mux_ff(
clk,
in,
out_pos,
out_neg
);
input clk;
input in;
output out_pos;
output out_neg;
wire clk;
wire in;
reg out_pos;
reg out_neg;
reg pos_reg,neg_reg;
always @ (clk or in)
begin
pos_reg = ~ clk ? in : pos_reg ;
out_pos = clk ? pos_reg : out_pos ;
end
always @ (clk or in)
begin
neg_reg = clk ? in : neg_reg ;
out_neg = ~ clk ? neg_reg : out_neg ;
end
endmodule
correct me if i am wrong.....thanks