Porting of verilog assign/always@(*) statement to UVM

Status
Not open for further replies.

Yankie

Newbie level 4
Joined
Dec 12, 2012
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,345
Hi,

I am trying to port always@(*) blocks in my verilog environment to UVM.

E.g always @ (*)
begin
a = tx_intf.A;
b = ~a;
end

task gen;
@(posedge clk);
if(b) -----
@(posedge clk);
c = b;
and so on...
endtask
where,
tx_intf -> Interface

What is the recommended practice to port the above always@(*) block to UVM class?

I was thinking of calling following function:
function abc
a = tx_intf.A;
b = ~a;
endfunction

task gen;
@(posedge clk);
abc();
if(b) -----
@(posedge clk);
abc();
c = b;
and so on...
endtask

Could you please suggest a better way?

Thanks !
 

A better way depends on how often you need to reference these signals versus how often they change their values. You don't want to be executing the same code over and over if the result rarely changes. And if the result changes often, but you rarely need these variables, then you will be wasting time computing them Also, if there are a lot of variables, how dependent are they on each other?

So it is difficult to give you a better answer without knowing more specifics of what you a re trying to do, but here are some general suggestions:

If you can keep the always_comb and assign statements in the interface, that would probably be the most efficient.

Create get_variable methods for variables you rarely need, and call the method instead of accessing the variable. for example

Code:
function bit get_b();
   return ~tx_intf.A;
endfunction
task gen;
  @(posedge clk);
if(get_b()) -----
@(posedge clk);
   c = get_b();
 
Reactions: Yankie

    Yankie

    Points: 2
    Helpful Answer Positive Rating
Thanks Dave !

The interface is being used by many other modules. Also, the functionality of always@(*) is specific to my module. So I am less inclined towards moving always@(*) to the interface.

The number of variables in always@(*) are just 3 or 4. However, these variables are being used in multiple places and also required to be evaluated often in the code (almost every clk or alternate clk).

Thanks !
 

Another option is to use fork/join_none to spawn a process that acts like an always block. This is not very effecient, so keep the number of these kinds of processes to a minimum.

Code:
task run_phase(uvm_phase phase);
fork
   forever @(tx_intf.A) b = ~ tx_intf.A;
join_none
...
endtask

There is a site for UVM help at https://verificationacademy.com
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…