Poor Clock tree - how to overcome that?

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jitendravlsi

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Poor Clock tree

If you are facing a unnecessarily long latency from pll to sync pin because of blockage over macros in between, which deviates the shorter path into a long path, then how will you overcome this problem? Clock bufs are used in this path but not achieving the target latency.
 

Re: Poor Clock tree

waiting for reply....................
 

Re: Poor Clock tree

Hi,
maybe you should place your PLL near corresponding "cloud of logic", where u need do CTS?
Maybe you should give enough place between your macros for CTS buffer insertion?
Maybe you do not allow CTS-tracer use upper metal over those blockages above macros?
Is there any congestion before routing of your trees?

Also u need to analyze: is there enough buffers (and simply "long road" to your sinks, too many stages) or you expect more buffers in your trees and there is losses in long traces.

btw, sorry for my English.
 

    jitendravlsi

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Poor Clock tree

why dont u use feedthrough clock tree option
 

    jitendravlsi

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Re: Poor Clock tree

Dear Raju,

please tell me what is this " feedthrough clock tree option " ?

and how it will help in this case?


can i go for soft blockage instead of hard blockage over macros or for the space between macros?


thanks
jit
 

Poor Clock tree

as far as i remember hard blockage means absolute prohibition for placement in certain areas.
soft blockage means initial prohibition for placement, but allows placement of buffers on optimization steps.
so you should put _soft_ blockage between your macros to allow CTS to place buffers there.
 

Poor Clock tree

yep, soft blockage also helps u, but in the placement clock tree will be ideal, and so placement engine may place other buffers thier, but definatly there is a scope to improve with soft blockage.

feebthrogh is just like a feedthrough path from the hardblock, if there is a scope to insert these paths in the hardblockage (in2out paths)
 

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