Polysilicon capacitor simulation

Hi everyone,

I'm trying to simulate polysilicon capacitors. The main idea is to know the mismatch after MC simulation.
Unfortunately, I'm not sure to understand how polycaps work!For metal-metal, it's quite linear so simple sinwave can give the current and voltage and then deduce the capacity. For MC sim, a simple dc source with capacitor divider provides the divided voltage variation = mismatch.
What abt polycap? When I'm sweeping the voltage from -1 to 3V with a 1mV sinewave, I'm not able to get the same voltage, so the capacitance is continously changing! And even calculation from the current, voltage and frequency, I'm not able to find the 1pF settings.

Any Idea?

thks

Which polysilicon capacitors? Polysilicon to polysilicon (double poly process), or polysilicon to silicon with gate oxide in between (MOSCAP)?

In the latter case the strong cap change is normal when crossing the threshold voltage from depletion to inversion or accumulation.

I don't know but I should check... I guess it's a poly to silicon (kind of a MOS with D, S and B shorted together). So for sure it's normal if it's change, but I'm just wondering how to simulate, what kind of test bench to know the value of this capacitor. And if the capacitance depends on the voltage, is it possible, or too tricky to use it in an integrator, of swiched capacitor filters or in some kinds of applications where the voltage vary?

Thanks

Fabien said:

... if the capacitance depends on the voltage, is it possible, or too tricky to use it in an integrator, of swiched capacitor filters or in some kinds of applications where the voltage vary?

Click to expand...

In such case I'd suggest to use 2 anti-parallel MOSCAPs, s. the last 2 pages of the PDF. Of course you have to live with the ≈20% cap. rise between -1V and +1V (both caps contribute their depletion capacitance).

OK, thank you very much for your document and help. I'll try some simulations tomorrow.
But, it means that I should avoid to use the capactor below the threshold? And be sure to use it outside of the {-1 ; 1}V range?!

Fabien said:

... it means that I should avoid to use the capactor below the threshold? And be sure to use it outside of the {-1 ; 1}V range?!

Click to expand...

This depends totally on your circuit. Usually a +20% capacitance change doesn't matter in SC applications, nor in a feedback (Miller) compensation application. Of course you shouldn't use such a cap in a frequency determining filter or measuring application.

MOSCAPs can be used as varactors, however (voltage to frequency control).

Thank you, everything is clrearer by now!
Actually, I first simulated some capacitors in my library, but the leakage changes regarding the voltage applied to the capacitor, but also the capacitance change! On the plot "Capacitor_impedence_vs_voltage", I simulate a DC ramp from -3 to 3V with a sinewave of 1mV. We can see the leakage (average current) never constant, and the capacitance (corresponding to the peak to peak current) changing but almost constant after 1.5V. Nevertheless, after 1.5V, the capacitance measured is different from the settings! Any idea what kind of cap it could be? For me it's also polycap.

Anyway, I abord these capacitances and found the right one you suggested. The plot for the P one is presented and it could be quite constant if the voltage doesn't change too much. I also simulated the P and N in parallele and got this last plot. The difference of the capacitance is 11%! As my project is for measurements, I'll keep the design with MIM capas, but I'm not sure that my boss will accepte to buy the metal mask!

I tried antiparallele with P type capacitors, and it's quite better (6.5%)
thanks once again

Poly depletion is a problem, and it varies w/ species, foundry
flow and so on. A poly-poly cap may not care about polarity
if the two poly sheets are the same. A metal-poly (or poly-
epi) cap will have depletion asymmetry. Whether or not these
are realistically modeled, particularly their variation, depends
on how much your foundry cares - and your MC analysis is
only as good as this, at best.

OK, I understand. But how to explain the variation of the leakage regarding to the polarity? (see the snapshot)

I guess this is dispersion current (in the transition region to accumulation?). Dispersion of mobile charge carriers in the oxide/silicon junction.

Fabien said:

OK, I understand. But how to explain the variation of the leakage regarding to the polarity? (see the snapshot)

Click to expand...

If the leakage current is real, and is tunnelling based, then
surface roughness at the interfaces is likely an actor (like
electron-throw from a pointed tip is greater than from a
more relaxed curvature). The top surface of the lower plate
is unlikely to be identical to the bottom surface of the upper,
in material, interface qualities or chemistry (work function).

That's one theory for you, anyway. But I'd still be looking
for some data based validation, because models lie.