polyphase filter-decimator on VHDL: some troubles

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breezey

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Hello to all! I have wrote the polyphase filter-decimator on VHDL, decimation factor M is 6.
The testbench showed decimation, but data in the out bus is not correct. Can someone look on my code and get an advice to me how i can fix troubles in it and what is it troubles? I have attached txt files with codes of the filter and his testbech.
 

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  • testbench.txt
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Problems where it compiles but there is a problem in the code is really a problem for you to debug. If there is a problem like this - trace back the values through the sime. So from the output, look at the output drivers, followed by their drivers etc. Then check each stage to see if it is producing expected values.

as a side note - any reason you have used the non-standard std_logic_arith package rather than the standard numeric_std?
 

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