PNP deviation in CMOS process

[jackyhsu]

Dear All:

Paracitial PNP device is generally used in analog design .But I find it's deviation too large (about +/- 10% when 97% samples cover) . does anyone have the same experience or suggestion when PNP must be used?

Emitter area:10x10um
Process:0.35um/0.5um

thanks..

 

[ambreesh]

Could you please elaborate what deviations are u talking about.
Is it Vbe or Is(saturation current)

 

[Vamsi Mocherla]

Yes,it is a general trend that parasitic PNPs varyabout 10 % over the corners. Actually if you look in your SPICE decks, you will see those variations. It all depends on how good a process you are using.

 

[jackyhsu]

Deviation means "spreading" not process corners differnce.
Out test pattern is to feed constant current(uA) and measure Vbe.

Thanks.

 

[ambreesh]

Can i interpret that, your Vbe varies by 10% from sample to sample on same wafer.
And, the samples, are they distributed all over the wafer or are the localised from one area.
And if your Vbe is varying by 10% then I cannot imagine Is varation (for fixed Ic) as Vbe is inversly proportional to natural logarithm of Is ( which we all know well).