warlocklw
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For an inverter, PMOS is at top and NMOS bottom. Vdd provide voltage to PMOS.
Lets say node A is node where Vdd and PMOS source join,
when DC analysis is performed at the gate input,
the leakage current will peak at Vin=Vout.
Node A will be a negative current, since PMOS current is negative when turned on.
So, since P=VI, the DC analysis is positive voltage of 0 to 1V,
will the power also negative?
How is possible that power is negative, since it means we gain more power by turning on the device.
Any idea? Thanks.
Lets say node A is node where Vdd and PMOS source join,
when DC analysis is performed at the gate input,
the leakage current will peak at Vin=Vout.
Node A will be a negative current, since PMOS current is negative when turned on.
So, since P=VI, the DC analysis is positive voltage of 0 to 1V,
will the power also negative?
How is possible that power is negative, since it means we gain more power by turning on the device.
Any idea? Thanks.