swolf
Newbie level 6
hi all
I have a problem when I design a sampling circuit. The sampling cap is very big, so the switch (which is a CMOS switch) resistance should be very low to get a good sampling presicion. but the PMOS size is very big to get a low resistance.
The bootstapped switch is not suitable because there are a lot of capacitors.
Normally, the PMOS bulk is connected to the VDD.
How about it if I connect the bulk of PMOS to its source to lower its Vth so the PMOS size could be smaller? I saw it in some paper which said that the bulk is connected to its source when it is in sampling phase and to Vdd when in hold phase.
I am not sure about it. Can anyone give me some hints? Thank you very much.
I have a problem when I design a sampling circuit. The sampling cap is very big, so the switch (which is a CMOS switch) resistance should be very low to get a good sampling presicion. but the PMOS size is very big to get a low resistance.
The bootstapped switch is not suitable because there are a lot of capacitors.
Normally, the PMOS bulk is connected to the VDD.
How about it if I connect the bulk of PMOS to its source to lower its Vth so the PMOS size could be smaller? I saw it in some paper which said that the bulk is connected to its source when it is in sampling phase and to Vdd when in hold phase.
I am not sure about it. Can anyone give me some hints? Thank you very much.
