PMOS sleep transistor driving capacitance

[kingslayer]

Dear all,

here is the scenario: I use PMOS header sleep transistors and I want to estimate the time required to drive the load capacitance. Basically, I am interested in the case when the control signal on the Gate is logical 0, the input (acting as a Source) is Vdd and the output (with the load capacitance) goes from 0V to Vdd. I have to derive the expression by and since I need the closed-form expressions.

If I am not wrong, the PMOS transistor will first be in saturation region, up to the time when the voltage on the capacitance equals Vt (in modulus); after that point the transistor is in linear region and the current magnitude decreases over time. In the first case it is quite easy to derive the expression, but in the second case I have some problems, since the V_DS changes over time, and I don't know which is the shape of this function (could I assume it to be exponential since it is basically dependent on the change of the voltage on the load capacitance?).

Could anyone please guide me along this?

Thanks in advance
Cheers