Do you think you know more about the downsides of
injecting well current, than the foundry does? This
is why, the rule. If you're going to do things that are
unproven or known bad ideas, then they want to make
sure you are forced to justify it before accepting the
mask art. Otherwise it's a bunch of boo-hoo-hoo when
the circuit latches up, and the finger points at them
and costs them engineering support hours while you try
to pin it on anything at all besides your own bad idea.
For a "test chip" you could probably get the rule violation
waived, if you provide justification and accept all of the
responsibility. For real product I would expect you'd need
to qualify this abnormal application (forward body bias)
unless the foundry has plowed that road for you. And then
there would still ought to be application rules, such as
maybe you need to put I/O-rules guard rings around any
well that is forward biased to its contents to inhibit core
latchup (where you enjoy lighter layout penalties based on
the assumption that you tied everything down in the normal
fashion, max tap spacing and all that).