[SOLVED] plzz help me debug this verilog code of simple microprocessor........................

module AC ( input [15:0] data_in, input load, clk,
output reg [15:0] data_out );
always @( posedge clk or negedge clk )
if( load ) data_out <= data_in;
endmodule

module ALU_REG ( input [15:0] data_in,input clk,
output reg [15:0] data_out );
always @( posedge clk or negedge clk )
data_out <= data_in;
endmodule

module psw_reg ( input [2:0] data_in, input clk,
output reg [2:0] data_out );
always @( posedge clk or negedge clk )
data_out <= data_in;
endmodule

module PC ( input [9:0] data_in, input load, inc, clr, clk,
output reg [9:0] data_out );
always @( posedge clk )
begin
if( clr ) data_out <= 10'b00_0000_0000;
else if( load ) data_out <= data_in;
else if( inc ) data_out <= data_out + 1;
end
endmodule

module IR ( input [15:0] data_in, input load, clk,
output reg [15:0] data_out );
always @( posedge clk )
if ( load ) data_out <= data_in;
endmodule

module REG_B ( input [15:0] data_in, input load, clk,
output reg signed [15:0] data_out );
always @( posedge clk or negedge clk )
if( load ) data_out <= data_in;
endmodule

module REG_C ( input [15:0] data_in, input load, clk, inr_c, dcr_c,
output reg [15:0] data_out );
always @( posedge clk or negedge clk )
begin
if(load) data_out <= data_in;
else if (inr_c) data_out <= data_out + 1;
else if (dcr_c) data_out <= data_out - 1;
end
endmodule

module REG_D ( input [15:0] data_in, input load, clk, inr_d, dcr_d,
output reg [15:0] data_out );
always @( posedge clk or negedge clk )
begin
if( load ) data_out <= data_in;
else if (inr_d) data_out <= data_out + 1;
else if ( dcr_d ) data_out <= data_out - 1;
end
endmodule

//ALU module
module ALU_MP ( input [15:0] a, b,
input pass, add, sub, adc, sbb, rsb, cmp,
ana, ora, xra, sla, sra, inr, dcr, tcp,
ral, rar, mul, div, cma, rsc, rsz, rsf,
output reg [15:0] alu_out,
output reg [2:0] psw );
reg [15:0] temp;

always @(a or b or pass or add or sub or adc or sbb or rsb or cmp or ana or ora or xra
or sla or sra or inr or dcr or tcp or ral or ral or mul or div or cma or rsc
or rsz or rsf or alu_out or psw )
begin
if (pass) alu_out = a; //pass a out
else if (add) begin
{psw[2],alu_out} = a + b; //add
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);

end
else if (sub) begin
{psw[2],alu_out}=a - b; //sub
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);

end
else if (adc) begin
{psw[2],alu_out} = a + b + psw[2]; //add with carry
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (sbb) begin
{psw[2],alu_out}=a - (b + psw[2]); //sub with borrow
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (rsb) begin
{psw[2],alu_out}=b - a; //reverse sub
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (cmp) begin
alu_out= ~a; //complement
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (ana) begin
alu_out=a & b; //and
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (ora) begin
alu_out =a | b; //or
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (xra) begin
alu_out =a ^ b; //exor
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (sla) begin
alu_out =a << 1; //shift left a
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (sra) begin
alu_out =a >> 1; //shift right a
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (inr) begin
alu_out =a + 1;
psw[2]=1'b0; //increment a
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (dcr) begin
alu_out =a - 1; //decrement a
psw[2]=1'b0;
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (tcp) begin
alu_out =(~a)+1; //two's complement of a
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (ral) begin
alu_out ={a[14:0],a[15]}; //rotate accu left
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (rar) begin
alu_out ={a[0],a[15:1]}; //rotate accu right
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (mul) begin
alu_out =a[15:0]*b[15:0]; //multiply
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (div) begin
alu_out =a / b; //division
psw[2:1]=2'b00;
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (cma) begin
{psw[2],temp} =a - b; //compare
psw[1]=alu_out[15];
psw[0]=~(alu_out[0]|alu_out[1]|alu_out[2]|alu_out[3]|alu_out[4]|alu_out[5]|alu_out[6]|alu_out[7]|
alu_out[8]|alu_out[9]|alu_out[10]|alu_out[11]|alu_out[12]|alu_out[13]|alu_out[14]|alu_out[15]);
end
else if (rsc) psw[2]=1'b0; //reset carry flag
else if (rsz) psw[0]=1'b0; //reset zero flag
else if (rsf) psw=3'b000; //reset flags

end
endmodule

//Data path
module DataPath ( input ir_on_adr, pc_on_adr, dbus_on_data,
data_on_dbus, ld_ir, ld_ac, ld_pc,
inc_pc, clr_pc, pass, add, alu_on_dbus,
clk, sub, adc, sbb, rsb, cmp,
ana, ora, xra, sla, sra, inr, dcr,
tcp, ral, rar, mul, div, cma, rsc, rsz, rsf,
mov_b, mov_c, mov_d, mov_a,
c_on_adr, d_on_adr,
inr_c, dcr_c, inr_d, dcr_d,
ld_rc, ld_rb, ld_rd,
output [9:0] adr_bus,
output [5:0] op_code,
inout [15:0] data_bus,
output [2:0] flags );
wire [2:0] psw_wire;
wire [15:0] dbus, ir_out, a_side, b_side, alu_out, d_out, c_out, alu_w;
wire [9:0] pc_out;

ALU_REG alu_reg ( .data_in(alu_w), .clk(clk), .data_out(alu_out) );

IR ir ( .data_in(dbus), .load(ld_ir), .clk(clk), .data_out(ir_out) );

PC pc ( .data_in(ir_out[9:0]), .load(ld_pc), .inc(inc_pc), .clr(clr_pc), .clk(clk), .data_out(pc_out) );

AC ac (.data_in( dbus), .load(ld_ac), .clk(clk), .data_out(a_side) );

REG_B reg_b ( .data_in(dbus), .load(ld_rb), .clk(clk), .data_out(b_side) );

REG_C reg_c ( .data_in(dbus), .load(ld_rc), .clk(clk), .inr_c(inr_c), .dcr_c(dcr_c), .data_out(c_out) );

REG_D reg_d ( .data_in(dbus), .load(ld_rd), .clk(clk), .inr_d(inr_d), .dcr_d(dcr_d), .data_out(d_out) );

psw_reg psw_i( .data_in(psw_wire), .clk(clk), .data_out(flags));

ALU_MP alu_mp ( .a(a_side), .b(b_side), .pass(pass), .add(add),.sub( sub), .adc(adc), .sbb(sbb), .rsb(rsb), .cmp(cmp),
.ana(ana), .ora(ora), .xra(xra), .sla(sla), .sra(sra), .inr(inr), .dcr(dcr), .tcp(tcp), .ral(ral), .rar(rar), .mul(mul), .div(div), .cma(cma), .rsc(rsc),
.rsz( rsz),.rsf( rsf), .alu_out(alu_w), .psw( psw_wire ) );


assign adr_bus = ir_on_adr ? ir_out[9:0] : 10'bzz_zzzz_zzzz;
assign adr_bus = pc_on_adr ? pc_out : 10'bzz_zzzz_zzzz;
assign dbus = alu_on_dbus ? alu_out : 16'bzzzz_zzzz_zzzz_zzzz;
assign data_bus = dbus_on_data ? dbus : 16'bzzzz_zzzz_zzzz_zzzz;
assign dbus = data_on_dbus ? data_bus : 16'bzzzz_zzzz_zzzz_zzzz;
assign dbus = mov_a ? a_side : 16'bzzzz_zzzz_zzzz_zzzz;

assign dbus = mov_b ? b_side : 16'bzzzz_zzzz_zzzz_zzzz;
assign dbus = mov_c ? c_out : 16'bzzzz_zzzz_zzzz_zzzz;
assign dbus = mov_d ? d_out : 16'bzzzz_zzzz_zzzz_zzzz;
assign adr_bus = c_on_adr ? c_out[9:0] : 10'bzz_zzzz_zzzz;
assign adr_bus = d_on_adr ? d_out[9:0] : 10'bzz_zzzz_zzzz;
assign op_code = ir_out[15:10];

//$monitor("dbus=%b", dbus);


endmodule


//controller module starts
`define Reset 3'b000
`define Fetch 3'b001
`define Execute 3'b011
`define Halt 3'b100
module Controller ( input reset, clk, input [5:0] op_code,
output reg rd_mem, wr_mem, ir_on_adr,
pc_on_adr, dbus_on_data,
data_on_dbus, ld_ir, ld_ac,
ld_pc, inc_pc, clr_pc,
pass, add, alu_on_dbus,
sub, adc, sbb, rsb, cmp,
ana, ora, xra, sla, sra, inr, dcr,
tcp, ral, rar, mul, div, cma, rsc, rsz, rsf,
mov_b, mov_c, mov_d, mov_a,
c_on_adr, d_on_adr,
inr_c, dcr_c, inr_d, dcr_d,
ld_rc, ld_rb, ld_rd, input[2:0] flags);

reg [2:0] present_state, next_state;
always @( posedge clk )
if( reset ) present_state <= `Reset;
else present_state <= next_state;
always @( present_state or reset ) begin : Combinational
rd_mem=1'b0; wr_mem=1'b0; ir_on_adr=1'b0; pc_on_adr=1'b0;
dbus_on_data=1'b0; data_on_dbus=1'b0; ld_ir=1'b0;
ld_ac=1'b0; ld_pc=1'b0; inc_pc=1'b0; clr_pc=1'b0;
pass=1'b0; add=1'b0; alu_on_dbus=1'b0;
sub=1'b0; adc=1'b0; sbb=1'b0; rsb=1'b0; cmp=1'b0;
ana=1'b0; ora=1'b0; xra=1'b0; sla=1'b0; sra=1'b0; inr=1'b0; dcr=1'b0;
tcp=1'b0; ral=1'b0; rar=1'b0; mul=1'b0; div=1'b0; cma=1'b0; rsc=1'b0; rsz=1'b0; rsf=1'b0;
mov_b=1'b0; mov_c=1'b0; mov_d=1'b0; mov_a=1'b0;
c_on_adr=1'b0; d_on_adr=1'b0;
inr_c=1'b0; dcr_c=1'b0; inr_d=1'b0; dcr_d=1'b0;
ld_rc=1'b0; ld_rb=1'b0; ld_rd=1'b0;
case ( present_state )
`Reset : begin next_state = reset ? `Reset : `Fetch;
clr_pc = 1;
end // End `Reset

`Fetch : begin next_state = `Execute;
pc_on_adr = 1; rd_mem = 1; data_on_dbus = 1;
ld_ir = 1; inc_pc = 1;
end // End `Fetch



`Execute: begin next_state = `Fetch;

case( op_code )
8'b00_0000: begin
ir_on_adr = 1; rd_mem = 1;
data_on_dbus = 1; ld_ac = 1;

end

8'b00_0001: begin
ir_on_adr = 1; mov_a = 1;
dbus_on_data = 1; wr_mem = 1;
end

8'b00_0010: ld_pc = 1;

8'b00_0011: begin
add = 1; alu_on_dbus = 1;
ld_ac = 1; dbus_on_data = 1;
end

8'b00_0100: begin
sub=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_0101: begin
adc=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_0110: begin
sbb=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_0111: begin
rsb=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1000: begin
cmp=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1001: begin
ana=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1010: begin
ora=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1011: begin
xra=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1100: begin
sla=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1101: begin
sra=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1110: begin
inr=1; alu_on_dbus=1; ld_ac=1;
end
8'b00_1111: begin
dcr=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0000: begin
tcp=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0001: begin
ral=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0010: begin
rar=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0011: begin
mul=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0100: begin
div=1; alu_on_dbus=1; ld_ac=1;
end
8'b01_0101: begin
cma=1;
end
8'b01_0110: begin
if(flags[2])
begin
ld_pc=1;
end

end
8'b01_0111: begin
if(flags[0])
begin
ld_pc=1;
end

end
8'b01_1000: rsc=1;
8'b01_1001: rsz=1;
8'b01_1010: rsf=1;
8'b01_1011: begin
ir_on_adr = 1; rd_mem = 1;
data_on_dbus = 1; ld_rb = 1;
end
8'b01_1100: begin
ir_on_adr=1;
data_on_dbus=1;
ld_rc=1;
end
8'b01_1101: begin
pass=1;
alu_on_dbus=1;
ld_rc=1;
end
8'b01_1110: begin
mov_b=1;

ld_rc=1;
end
8'b01_1111: begin
inr_c=1;
end
8'b10_0000: begin
dcr_c=1;
end
8'b10_0001: begin
mov_c=1;
ld_ac=1;
end
8'b10_0010: begin
mov_c=1;
ld_rb=1;
end
8'b10_0011: begin
pass=1;
alu_on_dbus=1;
ld_rb=1;
end
8'b10_0100: begin
mov_b=1;
ld_ac=1;
end
8'b10_0101: begin
c_on_adr=1;
rd_mem=1;
data_on_dbus=1;
ld_rb=1;
end
8'b10_0110: begin
ir_on_adr=1;
rd_mem=1;
data_on_dbus=1;
ld_rd=1;
end
8'b10_0111: begin
pass=1;
alu_on_dbus=1;
ld_rd=1;
end
8'b10_1000: begin
mov_b=1;
ld_rd=1;
end
8'b10_1001: begin
mov_c=1;
ld_rd=1;
end
8'b10_1010: begin
mov_d=1;
ld_ac=1;
end
8'b10_1011: begin
mov_d=1;
ld_rb=1;
end
8'b10_1100: begin
mov_d=1;
ld_rc=1;
end
8'b10_1101: begin
inr_d=1;
end
8'b10_1110: begin
dcr_d=1;
end
8'b10_1111: begin
d_on_adr=1;
rd_mem=1;
data_on_dbus=1;
ld_rb=1;
end
8'b11_0000: begin
next_state = `Halt;
end
8'b11_0001: begin
ir_on_adr=1;
mov_b=1;
dbus_on_data=1;
wr_mem=1;
end
endcase
end // End `Execute
`Halt: next_state = `Halt;
default: next_state=`Fetch;
endcase
end //end always block
endmodule

//top cpu module
module TopCPU (input reset, clk,
output [9:0] adr_bus, output rd_mem, wr_mem,
inout [15:0] data_bus);
wire ir_on_adr, pc_on_adr, dbus_on_data, data_on_dbus,
ld_ir,
ld_ac, ld_pc, inc_pc, clr_pc, pass, add, alu_on_dbus,
sub, adc, sbb, rsb, cmp,
ana, ora, xra, sla, sra, inr, dcr,
tcp, ral, rar, mul, div, cma, rsc, rsz, rsf,
mov_b, mov_c, mov_d, mov_a,
c_on_adr, d_on_adr,
inr_c, dcr_c, inr_d, dcr_d,
ld_rc, ld_rb, ld_rd;
wire[2:0] flags;
wire [5:0] op_code;
Controller cu ( .reset(reset), .clk(clk), .op_code(op_code), .rd_mem(rd_mem),.wr_mem( wr_mem ), .ir_on_adr(ir_on_adr),
.pc_on_adr(pc_on_adr), .dbus_on_data(dbus_on_data), .data_on_dbus(data_on_dbus), .ld_ir(ld_ir),
.ld_ac(ld_ac), .ld_pc(ld_pc), .inc_pc(inc_pc),.clr_pc( clr_pc),.pass( pass),
.add(add), .alu_on_dbus(alu_on_dbus),
.sub( sub), .adc(adc),.sbb( sbb),.rsb( rsb),.cmp( cmp),
.ana(ana), .ora(ora), .xra(xra), .sla(sla), .sra(sra),.inr( inr ),.dcr( dcr),
.tcp(tcp), .ral(ral), .rar(rar), .mul(mul), .div(div), .cma(cma), .rsc(rsc),.rsz( rsz), .rsf(rsf),
.mov_b( mov_b), .mov_c(mov_c),.mov_d( mov_d), .mov_a(mov_a),
.c_on_adr(c_on_adr),.d_on_adr( d_on_adr),
.inr_c(inr_c),.dcr_c( dcr_c),.inr_d( inr_d),.dcr_d( dcr_d),
.ld_rc(ld_rc),.ld_rb (ld_rb), .ld_rd(ld_rd), .flags(flags) );

DataPath dp ( .ir_on_adr(ir_on_adr),.pc_on_adr( pc_on_adr),.dbus_on_data( dbus_on_data ), .data_on_dbus(data_on_dbus),
.ld_ir(ld_ir),.ld_ac( ld_ac ), .ld_pc(ld_pc), .inc_pc(inc_pc),.clr_pc( clr_pc ), .pass(pass),.add( add),
.alu_on_dbus(alu_on_dbus), .clk(clk),
.sub(sub), .adc(adc),.sbb( sbb),.rsb( rsb), .cmp(cmp),
.ana(ana), .ora(ora), .xra(xra), .sla(sla),.sra( sra ),.inr( inr),.dcr( dcr),
.tcp(tcp),.ral( ral), .rar(rar), .mul(mul),.div( div ), .cma(cma), .rsc(rsc), .rsz(rsz), .rsf(rsf),
.mov_b(mov_b), .mov_c(mov_c), .mov_d(mov_c), .mov_a(mov_a),
.c_on_adr(c_on_adr), .d_on_adr(d_on_adr),
.inr_c(inr_c), .dcr_c(dcr_c), .inr_d(inr_d), .dcr_d(dcr_d),
.ld_rc(ld_rc), .ld_rb(ld_rb), .ld_rd(ld_rd),
.adr_bus(adr_bus), .op_code(op_code), .data_bus(data_bus), .flags(flags) );
endmodule

//Test bench
module Test_CPU;
reg reset=1'b1, clk=0;
wire [9:0] adr_bus;
wire rd_mem, wr_mem;
wire [15:0] data_bus;
reg [15:0] mem_data= 16'bxxxx_xxxx_xxxx_xxxx;
reg [15:0] data_bus_dri= 16'bxxxx_xxxx_xxxx_xxxx;
reg control=0;
reg [15:0] ram[0:1023];
integer i;

TopCPU CPUTest (reset, clk, adr_bus, rd_mem, wr_mem, data_bus);
initial
begin
for (i=0; i < 1024; i = i + 1) // Setting individual memory cells to 0
ram = 0;
end

always #10 clk = ~clk;
always @(data_bus)
data_bus_dri = data_bus;


initial begin
$readmemb("init.dat",ram);
#20 reset=1'b0;
#2005;

for(i=0; i < 1024; i = i + 1)
$display ( "Memory [%d] = %b" , i, ram );
$stop;

end
always @(posedge clk) begin : Memory_Read_Write
control = 1'b0;
#1;

if (rd_mem) begin

mem_data = ram[adr_bus];
control = 1;


end
if (wr_mem) begin
ram[adr_bus] = data_bus;


end
end
assign
data_bus = control ? mem_data : 16'bxxxx_xxxx_xxxx_xxxx;

endmodule


opcode
000000 load
000001 store a
000010 jump
000011 add a and d
000100 sustract b from a
000101 add with carry
000110 substract with carry
000111 reverse substract(b-a)
001000 complement a
001001 AND
001010 OR
001011 X-OR
001100 shift left a
001101 shift right a
001110 increment a
001111 decrement a
010000 two's complement a
010001 rotate accumulator left
010010 rotate accumulator right
010011 multiply
010100 division(a/b)
010101 compare a and b
010110 jump on carry
010111 jump on zero
011000 reset carry
011001 reset zero
011010 reset flags
011011 load reg b
011100 load reg c
011101 mov a to c
011110 mov b to c
011111 increment c
100000 decrement c
100001 mov c to a
100010 mov c to b
100011 mov a to b
100100 mov b to a
100101 c on adr_bus and load data to b
100110 load reg d
100111 mov a to d
101000 mov b to d
101001 mov c to d
101010 mov d to a
101011 mov d to b
101100 mov d to c
101101 increment d
101110 decrement d
101111 load reg b
110000 halt
110001 store b address specified by last 10 bits

init.dat file contents Explanation of each opcode in file
@000
0000000000001111 load a from 00f
0110110000001110 load b from 00e
@002
0000110000000000 add a and b
0000010000001010 store a
1100000000000000 halt
@00e
1010101010101010 data at address 00e
0101010101010101 data at address 00f


OUTPUT
# Memory [ 0] = 0000000000001111
# Memory [ 1] = 0110110000001110
# Memory [ 2] = 0000110000000000
# Memory [ 3] = 0000010000001010
# Memory [ 4] = 1100000000000000
# Memory [ 5] = 0000000000000000
# Memory [ 6] = 0000000000000000
# Memory [ 7] = 0000000000000000
# Memory [ 8] = 0000000000000000
# Memory [ 9] = 0000000000000000
# Memory [ 10] = xxxxxxxxxxxxxxxx
# Memory [ 11] = 0000000000000000
# Memory [ 12] = 0000000000000000
# Memory [ 13] = 0000000000000000
# Memory [ 14] = 1010101010101010
# Memory [ 15] = 0101010101010101


PLZ PLZ HELP ME IN DEBUGGING THIS CODE....

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