Plz. I want to use *.vcd or *.vec file in Verilog HDL

[CY.Lim]

Hi. All.
I'm sorry. I don't write english very well...

I designed Circuit and to make TEST Module for verification using Verilog HDL.
TEST Module's input type is *.vcd or *.vec file.

*.vcd type                                                      |  *.vec type 
$scope module TOP $end                                          | TIME ADJ_BUF CLK_SK[2:0] 
$var wire 1 ! ADJ_BUF $end                                      | 2.910E-03 1 110
$var wire 3 " CLK_SK[2:0] $end ( maybe wire name and Bus .. )   | 2.913E-03 1 101
...                                                             |
$enddefinitions $end                                            |
#2910293876 ( maybe time... )                                   |
0!                                                              |
0" ......

My Test Module is..

---

Code Verilog - [expand]
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`timescale 1ns / 1ps 
`include " ~ "
module top ; 
reg ~ 
initial ~ 
wire ~ 
wreal ~ 
initial begin ~ 
end 
initial begin
&shm_open("~");
$shm_probe("AC") 
end
endmodule

---

Problem is ....
1. Can I enter *.vcd or *.vec file into the TEST Moulde.
2. *.vcd is declared a port (wire) but *.vec is not. How do I declare port?

If anyone knows about this problem, I hope you can help me.
Thx for reading the long question.

 

[ads-ee]

Honestly I'm not sure what you are trying to accomplish here, but using verilog as a parser for vcd is not what you want to do. Here is a site with some PLI routines and one of them happens to be a VCD reader.

I have no clue what the contents of a .vec file are so I can't even fathom if you could read it into Verilog, but like I said already, Verilog makes a really poor parser. Use C or some scripting language like Python/Perl to change the .vec file into something you can read from Verilog, or start searching for a .vec PLI reader (nothing comes up when I searched for that).

 

[CY.Lim]

I didm't find the category. but thank you for your help.

 

[CY.Lim]

plz. I want to use *.vcd or *.vec file type input data in Verilog HDL

Hi. all.

I'm sorry. I don't english good well.

I designed circuit and to make TEST module for varification using Verilog HDL.
TEST module's input data is *.vcd or *.vec file.

-----------------------------------

---

Code Verilog - [expand]
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*.vcd file
$scope module TOP $end
$var wire 1 ! name1 $end
$var wire 8 " name2[7:0] $end
...
$enddifinitions $end
#1234 
0!
0 "
...
-----------------------------------
*.vec file
TIME name1 name2[7:0]
1234 1 11111111
1235 1 11111110
....
-----------------------------------

---

My TEST Module is ...

-----------------------------------

---

Code Verilog - [expand]
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`timescale 1ns/1ps
`include " ~"
module top;
reg~
real~
wire~
wreal~
....
endmodule

---

-----------------------------------

Problem is..

1. Can I use *.vcd or *.vec file in Verilog HDL into the TEST module ?

If anyone knows about this problem, I hope you can help me.

:sad::sad::sad::sad::sad::sad::sad::sad::sad:

 

[ads-ee]

I didm't find the category. but thank you for your help.

What? I don't understand what you are referring to by "category". What is that in reference to?