plz help....my project submission date is very near..

[john6794]

Dear during compilation of "implementation of asynchronous FIFO implementation in vhdl" program the following components are missing..

BUFGP
MUXCY_L
RAMB4_S8_S8

Plz send me vhdl program of those components.

And plz also tell how to incorporate those programs so that I am able to run my program.plz


program is also attached

 

[rberek]

These are Xilinx primitives, and you can find them in your Xilinx install directories

(i.e. xilinx/v8.2/vhdl/src/unisims/unisim_VCOMP.vhd)

Your location and Xilinx version will vary.

When you ask how to incorporate them into your "program", you really should mention which program you're talking about.

 

[echo47]

I'm guessing the errors occur during ModelSim simulation. That's a common problem if you haven't yet compiled the Xilinx simulation libraries (refer to the ISE "Synthesis and Simulation Design Guide"). Difficult to say for sure without knowing which software tools are involved.

 

[john6794]

dear thanks.yes those all are primitive.and now i have complied it and got just one warning.its ok.
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks