If the design will map and route without the ChipScope stuff, but fails when you attempt to include ChipScope, then I believe you have run out of resources within the FPGA. Xilinx has had a bug where they do not correctly calculate the required resources during the synthesize phase. When it gets into MAP, it cannot place all the logic and after several phases, it crashes. The end of synthesis should report a percentage of utilization. This number can often be over 100, as some logic reduction and trimming will occur in MAP. However, if it cannot be reduced to less than 100% later, it will crash.