Plz help me in synthesizing the D-FF.

Plz help me in synthesizing the D-FF.
This s the code which is i m synthesizing in ISE WebPACK


module dff(
Clock,
D,
Reset,
Q
);


parameter CARDINALITY = 1;


input Clock;
input [CARDINALITY-1:0] D;
input Reset;
output [CARDINALITY-1:0] Q;


wire [CARDINALITY-1:0] D;
reg [CARDINALITY-1:0] Q;
wire Clock;
wire Reset;


always @ (posedge Clock)
begin : process0
if (Reset !== 0) begin
#1 Q = D;
end
end


always
begin : process1
wait (Reset == 0);
Q = 0;
wait (Reset == 1);
end

endmodule


**********************************************************************TThis s the error which is displayed while i m synthesizing it in ISE WebPACK

ERROR:Xst:850 - "dff.v", line 46: Unsupported exactly not equal expression.
ERROR:Xst:850 - "dff.v", line 55: Unsupported Wait Statement.
ERROR:Xst:850 - "dff.v", line 57: Unsupported Wait Statement.

hi !

try this:
module dff (d, clk, rst, q);

input d, clk, rst;

output q;

reg q;

always @ (posedge clk)

if (rst == 1)
q <= 0;
else q <= d;

endmodule


good luck, bart