pls. help to explain the abnormal phenomina in silicon test

[chang830]

There is a compator which is flollowed by two inverters chain to provide a +/1 indicator signal. The power supply is 3.3V and the process is TSMC 0.25um cmos. To my supprise, in testing, the chip one showed that the output high is
only 2.02 V,the output low is 0.87V. I test other samples, all others is OK, they gives the correct output high 3.3V and low 0V.


Anyone pls. tell me what's the possible cause? Is it possibel caused by the ESD issue?

Thanks a lot

 

[nathan80]

Re: pls. help to explain the abnormal phenomina in silicon t

it could be due to esd strike on the ic as only one sample is showing a voltage drop and the other are not.

you can check whether this is due to esd strike is ; by allowing more current to flow. your testing is showing a voltage drop probably because you are limiting your current as the esd striked ic draws higher current. so allow more current to flow into the evaluation board and you will not see any drop of voltage.


usually if the ic has had complete esd strike it should not draw any current. except little current to power up the evaluation board.

 

[chang830]

Re: pls. help to explain the abnormal phenomina in silicon t

it could be due to esd strike on the ic as only one sample is showing a voltage drop and the other are not.

you can check whether this is due to esd strike is ; by allowing more current to flow. your testing is showing a voltage drop probably because you are limiting your current as the esd striked ic draws higher current. so allow more current to flow into the evaluation board and you will not see any drop of voltage.


usually if the ic has had complete esd strike it should not draw any current. except little current to power up the evaluation board.

Thanks for the replies.
My ic is not completely esd striked because the other pins is OK. So I doubt the esd issue for these two inverters output pins. As for ttesting if it is indeed caused bu the esd issue, how can I allow more current to flow into my EVB bord? It is voltaged supply?!

Could you clarify it a bit more? Thanks

 

[nathan80]

Re: pls. help to explain the abnormal phenomina in silicon t

Well, what i meant by increasing the current flow into the EV board does not mean you force in more current through additional circuitry.

I meant, your IC might be drawing higher current if it has ESD strike.

As an example, voltage supply on the EV board allows a maximum of 50mA. However, the IC + EV board draws around 85mA after ESD strike. So use a programmable power supply and adjust the maximum supplied current from 50 to 150mA. From my experience as a test engineer, voltage level drops if the voltage supply does not supply enough current.

This way you can really check if the IC is drawing higher current. If it is, one of the possibilities is ESD strike.

If still the problem exist, than it could be due to other factors.