read the book on MOS transistor and circuit design by kang...it has details about such structure...i.e.. how much every node charges by bcoz for MOS to conduct Vgs>Vt...apply this idea and u'l reach 2 da answer..
This circuit should conduct a perfect '1' and a bad '0'. Hence the output will be VDD when all the inputs are high and VTH above GND when the inputs will be zero. The rest of it is all timing information. The VTH of the which device is determined by the input timing information.
Added after 2 minutes:
Oh I am sorry that I did not notice the NMOS device. But the logic to be looked into is that PMOS is a bad conductor of zero and a good conductor of one and the opposite is the case for the NMOS.