Plotting parasitic capacitance with varying gate voltage

Hi,



I wanted to know, for an nMOS, how to plot CD as a function of VG. Specifically, I wanted to get the plot as in the Razavi book (pg no: 30) available here. I am planning to use LTSPICE for the purpose. Specifically pls. tell me how to connect the schematic and run the simulation.This will give me an idea as to how to capture changing parasitic capacitance through a simulation.



Any pointers will be thankfully acknowledged.



Thanks and Regards,

Arvind Gupta

I wouldn't recomend LTSpice for this, as (as far as I
have seen) support for scripting is not great. Maybe
it's just not popular.

What you want is to get the operating point capacitances
from the FET. That's probably a .measure statement of
some sort, the simulator has to support that access to
results (not just node voltages and port currents).

If you can get the result into a variable, then you can
print that variable to a file or even accumulate .OP
results in a vector and plot against the index (e.g.
the gate node voltage's source variable).

I know how to do this in NGSpice, but in LTSpice I have
no idea how to make it execute a file of my own creation.
It seems to want directives placed in the schematic as
texts. Maybe you can figure out a directive that causes
the script file you really want, to execute.

But since NGSpice has free Windows and Linux versions
(Windows as a good-to-go binary) and some degree
of LTSpice / PSPICE compatibility, if you must use LTSpice's
schematic capture then maybe you run the LTSpice netlist
in NGSpice where you can script things better?

MicroCAP12 is another good free option. LTSpice makes
things different for IC folks who want to put their fingers
in the details (oh, you wanted L, W, areas and peripheries
to make it all the way to the netlist? Too bad, the generic
FET symbols do not have those properties nor the means
to drive their evaluated values into the netlist as far as
I have seen. Although I know people who claim to have
sorted that out privately, LTSpice is a PCB oriented tool
which assumes you bought the discrete transistor you
wanted, and aren't trying to declare a variation on its
internal geometry. Maybe you can chase down the
methods for doing things IC-style. Me, I went and
chased down a friendlier open source schematics tool.

Below is my attempt to do it with LTspice for a Vgs of 0.1V to 10V (X-axis).
A right-click on the trace name allows you to insert arbitrary equations for that trace.
I believe that equation calculates the gate capacitance versus input bias at an arbitrary frequency of 1kHz.
Both the X and Y axis are set to linear display.
The Y-axis is labeled nA but that represents nF.