rishabh_31ec
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Hi I am plotting gm/Id vs Vgs and Id/w vs. Vgs for a PMOS as diode connected ( source and Body are connected to higher supply 1.8V , while gate and drain are connected to each other). Now a variable voltage supply Vg is connected between gate and ground and Vg varies from 0 to 1.8 volt.
Now my question is ,
whether these plots are also valid for a PMOS which is saturated but not in diode connected mode...
if not, then how can I plot this.
Foundry: tsmc. Process: 180nm
Now my question is ,
whether these plots are also valid for a PMOS which is saturated but not in diode connected mode...
if not, then how can I plot this.
Foundry: tsmc. Process: 180nm