PLL using thin oxide varactor in VCO

Dear All:

I am designing a conventional integer-N PLL in 40nm CMOS. In LC-VCO part the varactor is implemented by the thin oxide accumulated-mode MOS. When the PLL toward locked, the average current of charge pump output is nearly zero (nA level). However, I observe that the control line (Vctrl) of VCO keeps increasing steadily, though it is slow. I suspect it could be due to the leakage of thin oxide varactor. To verify, I simulate a standalone VCO with Vctrl connected to a resistor in serial of a capacitor. The initial value of cap is 0.6V. After free running of 2us, the voltage of cap increases as well. Could someone share experience about this? I am running another version using thick oxide but it takes time to simulate. What is normally the way to implement the varactor in LC-VCO?

Thanks and regards,

If the voltage keeps increasing while the PLL remains
locked and frequency remains on-setpoint, then you
have a mystery. But those two questions want a look.

If VTUNE movement does not show a corresponding
fOsc movement, then your oscillator is not voltage
controlled (like, maybe pinned or out of gas, frequency-
range-wise).

Thanks! I have another path for sub-harmonic injection locked to the VCO cross-coupled pair, and the normal PLL synchronized mechanism may fight with the injection locked toward their balance. Perhaps I should simulate longer to observer if they can reach at a steady state?

The details ought to be evident in the mixer output. Using harmonic mixing has a pull-in range limit depending on loop gain and the harmonic amplitude being reduced. DC feedback and drift must be controlled by some type II mixer feedback for absolute frequency range so that type I phase feedback takes over and dominates the VCO voltge to correct error within the harmonic lock-in range. This may require mixer gain switching within the loop between the two modes of absolute frequency error for desired output range and phase error within that range.

Without full details on the design, it is hard to be more explicit.

SunnySkyguy said:

The details ought to be evident in the mixer output. Using harmonic mixing has a pull-in range limit depending on loop gain and the harmonic amplitude being reduced. DC feedback and drift must be controlled by some type II mixer feedback for absolute frequency range so that type I phase feedback takes over and dominates the VCO voltge to correct error within the harmonic lock-in range. This may require mixer gain switching within the loop between the two modes of absolute frequency error for desired output range and phase error within that range.

Without full details on the design, it is hard to be more explicit.

Click to expand...

Thanks a lot!! I added 2pF capacitor at the harmonic mixer output and the Vctrl does not show increasing at the steady-state now. If no such damping capacitor, VCTRL goes up but the frequency does not change!! Besides, I have separated the PFD into PD and FD. At the beginning FD starts to eliminates the frequency error. Within the mixer (PD) lock-in range the FD shut down and the PD starts to take over the phase locking.
But I still dont understand why the 2nd harmonic causes VCTRL to increase even the frequency is locked?
Anyway, I am greatly impressed by your feedback and help.

NovelPanda said:

...
But I still dont understand why the 2nd harmonic causes VCTRL to increase even the frequency is locked?

Click to expand...

XOR PD always produces 2f out. but 90deg out of phase, so after FD lock which is edge sync'd, the transition to PD must shift 90deg. Perhaps this is what you mean by the Vctrl increase . ??

If the XOR PD has no cap at the output, the Vctrl always increases (though it is very slowly..) and seems no convergence reached. After I add about 2pF cap at the PD output, the Vctrl stop rising and convergence occurs.
In this case, the PD will continue to generate current to LPF if the FD has just locked the frequency. However, after a short time the PLL is still locked by the PD.

Yes storage cap for PD is essential for integrating phase error. Stability or jitter may improve in loop with gain control and lead-lag filter if necessary.