carl
Newbie level 3
Phase lock loop problem
Hi, every one,
I designed one PLL with 4046, the VCO is set at 8MHz with a exter divider of 1024, and the filter is a simple lead-lag filter.
Now the problem is the frequecy is locked well, but the phase between the SIG and COMP In changes when I change the input freuqency.
I suppose I need to change the filter to an active filter to make a type 2 system, so that there is no steady phase error. Is this right?
thanks in advance
Hi, every one,
I designed one PLL with 4046, the VCO is set at 8MHz with a exter divider of 1024, and the filter is a simple lead-lag filter.
Now the problem is the frequecy is locked well, but the phase between the SIG and COMP In changes when I change the input freuqency.
I suppose I need to change the filter to an active filter to make a type 2 system, so that there is no steady phase error. Is this right?
thanks in advance