PLL Phase Noise

[Antra_Saxena]

Hi,

We are using mixer in our design in which LO is driven by PLL that is taking reference clock of 48 MHz on board. The phase noise of PLL is degrading the EVM of the system.
With external LO frequency from VSG improves the EVM as phase noise of VSG is clean.

Please advise, what can be the possible solution or cause of phase noise in PLL.


Thanks.

 

[BigBoss]

There are many factors that effect the overall PLL Phase Noise of a system. But the most important one is the Phase Noise of the VCO then-relatively- Charge Pump. You have to verify that the Close-In Phase Noise or Far-away Phase Noise is more influencer.
External LO is probably is much cleaner compare to Internal PLL therefore you get better EVM.
If you're able to measure the Phase Noise of the VCO stand alone, you can understand where the problem is coming from. Increasing the Charge Pump Current might be a solution, PLL reference clock can be selected by a cleaner source etc.

 

[KlausST]

Hi,

It can be erronously jittery or you are talking about physicall unavoidable jitter.
We neither know about signal voltage, circuit,PCB layout, PLL type, jitter values, frequency ...

We are currently tipping in the dark.

Klaus

 

[D.A.(Tony)Stewart]

Show your VCO control signal with time and spectral domains. This will tell us what interference and/or resonance you are dealing with. Your description just won't cut it. Type II mixers are notoriously bad for PM but guaranteed lock. You may need to list your goals for PM and results with negative feedback to reference clock. Clean signal to "a flat line on ground" is critical for accurate capture with appropriate test methods (coax, good impedance, etc)\


You might want to consider Si530.

 

[D.A.(Tony)Stewart]

Achieving low phase noise comes down to defining how much noise is introduced from each source with a noise "budget" Please show your block diagram, layout and how you measure noise and your design specs for phase noise floor( if you have a target...)

 

[Antra_Saxena]

Achieving low phase noise comes down to defining how much noise is introduced from each source with a noise "budget" Please show your block diagram, layout and how you measure noise and your design specs for phase noise floor( if you have a target...)

Actually, in our design, we have a mixer in which LO has range from -6 to 6 dB to obtain perfect IF at output. LO is driven by PLL after passing few blocks including LPF and gain block. We are able to achieve power levels in this range, but EVM at IF is bad (around 30%). Once LO is directly generated from VSG, EVM is perfect. So, after checking PLL phase noise at the output of PLL IC, it is bad. So, we are considering this phase noise is degrading EVM. The reference oscillator has clock of 48 MHz (square wave) and hence seen odd harmonics in frequency domain. Are these affecting performance of PLL? How to improve PLL phase noise in order to get good EVM at IF.

 

[Antra_Saxena]

There are many factors that effect the overall PLL Phase Noise of a system. But the most important one is the Phase Noise of the VCO then-relatively- Charge Pump. You have to verify that the Close-In Phase Noise or Far-away Phase Noise is more influencer.
External LO is probably is much cleaner compare to Internal PLL therefore you get better EVM.
If you're able to measure the Phase Noise of the VCO stand alone, you can understand where the problem is coming from. Increasing the Charge Pump Current might be a solution, PLL reference clock can be selected by a cleaner source etc.

In PLL IC, how can we check VCO stand alone phase noise? Yes, we are checking with external clock to see performance. Also, since clock is a square wave, we are seeing odd harmonics in frequency domain. Are these affecting the performance or these are obvious?

 

[BigBoss]

In PLL IC, how can we check VCO stand alone phase noise? Yes, we are checking with external clock to see performance. Also, since clock is a square wave, we are seeing odd harmonics in frequency domain. Are these affecting the performance or these are obvious?

If there is a possibility, disconnect the VCO Tuning Input and let the VCO in free oscillation.
If the oscillator output is available, measure the phase noise by Phase Noise Analyzer. Otherwise, if this is not possible, a small simple copper wire formed as loop will catch the oscillation due to radiation. If you draw close this small antenna over VCO, you can measure the signal even it's weak.
I tried this method in a integrated VCO over package and succeed.
Square waves have already odd mode harmonics because of its nature. No surprise.
You have to check two things.
-Free running oscillator (VCO)
-Reference Clock ( for PLL)
They are very dominant on overall Phase Noise of a system.
I presumed that PLL Lopp Filter has been very well designed and any other noise sources are negligible.

 

[D.A.(Tony)Stewart]

Bode plots are used to measure PLL phase or gain margin which can destroy PLL when there is insufficient phase lead compensation. Since you have no data, plots or details, I cannot be more specific.