Thanks for your help in advance.
My reference clock is 20MHz,charge pump current is 50uA, Kvco is 380MHz/V,divider N is 12. I select loop bandwidth of 1.5Mhz, and the simulated trans and pnoise is as below. From the trans, the system is stable. But in the pnosie figure, I don't know why the curve increase from 100k to 1M. Does it make sense?
Thank your reply.
That is because the PLL bandwidth is lower than the optimum intersection point of flat reference phase noise and 1/f vco phase noise. There is a similar effect if the PLL loop has low phase margin. In this case the peaking is looking a little different and the phase noise is not dropping so much before the peak.
The optmimum intersection frequency is where the multiplied reference noise cross the 1/f noise. Typical that give lowest overalll EVM which I think is important for DVBT.
Could you tell me how to simulae PNOISE?
Do you run all the circuit or using behavior model?
It seems to take a lot of time to wait PLL to be locked.
Do you take much time to get the result?
Dear rfsystem, thanks for your reply.
As you said, the pll bandwidth is lower and I should make it a little bigger, is it right? I should
fine tune the loop filter parameters R C1 and C2 (third order system)? Would you like to give me
some suggestion? Thank you very much.
Dear suederb, I simulated the pll with transitor level. I run pss and pnoise to get the phase noise
result. Some reference can be get from designers-guide. Thank you.
hi,wan,
Is your simulator Hspice? I don't find the pss and pnoise command.
In hspice,we know how to measure a sinewave's phase. But in digital PLL, the output is a square wave. How do you measure it?
Hi Wan,
Do you also combine the Xtal oscillator?
It seems that you simulation PNoise with Xtal Osc,
since the low frequeny noise?
Am I right?
In my experience, it takes several days to get the
loop stabe. you must have a good workstation.
hi wan,
can you tell me the positions of the zero and the third pole of the loop,
i think, the peaking is due to the small daming factor.
thanks
jeff.yan
hi,jeff
the damping factor is 1, from the trans simulation, settle is good.
zero is 0.4M,the third pole is 4.2M,loop bandwidth is 1.5M.Do you think it is suitable?
thanks
Hi Jeff,
I understand your point. From Thomas Lee's paper on JSSC 2000, PM is only a function of c1/c2 and the crossover frequency ωc=((b+1)**½)/τ. According to his formula, i calculate the parameters with my design value, PM is 56.4•,ωc=1.3M.I think PM maybe is not a issue.
Thanks for your suggestion, welcome to discuss further.
I upload the paper.
Hi Jeff,
I understand your point. From Thomas Lee's paper on JSSC 2000, PM is only a function of c1/c2 and the crossover frequency ωc=((b+1)**½)/τ. According to his formula, i calculate the parameters with my design value, PM is 56.4•,ωc=1.3M.I think PM maybe is not a issue.
Thanks for your suggestion, welcome to discuss further.
I upload the paper.
hi wan,
thanks. i am very glad to discuss the pll design topic with all of you.
i have other two questions:
1, is the peaking in phase noise curve identical to the jitter peaking,which can be reduced by increasing the damping factor(>1);
2, from the control voltage curve, i found the ripple is a little large, righ
what's your oscilator type, ring-osc?
b.s
jeff
Hi, Jeff
From some reference, it is recommended that the dampling factor is set to 1. And I think i cannotget the jitter peaking from simulation. I can only get the pnoise.
I used ring oscillator
thanks