Hawaslsh
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Hello all,
I am working to design a duel pll clocking scheme and I am playing around with Ti's PLLatinum software and ADI's ADIsimPLL software. In order to design the first PLL which uses a VCXO as the oscillator I need to know certain parameters of the VCXO. The first parameter I need to know is the tuning sensitivity (Kvco) in MHz/V.
Using the above datasheet as an example. I am given the sensitivity in ppm/V. To convert the ppm/V to MHz/V would I simply multiply my the VCXO's intended frequency, 100MHz in this case, and divide by 10^6? Giving me a sensitivity of 0.0025 MHz / V?
I also need to know the VCO capacitance. The datasheet give me a load capacitance, but is that the same capacaitance the PLL softwares are asking for? It doesn't seem right using the capacitance from the VCXO output characteristics as the VCOcap. Especially since the ADI software shows that capacitance at the input of the VCO.
Lastly. All of the clocks I need to generate share 100 MHz has their least common factor, so i planned on the first pll in the duel pll system to produce 100 MHz. Is there any issues using a 100 MHz reference to try and lock my 100 MHz VCXO to? Would it be better to use a different reference frequency?
Thanks in advance,
Sami
I am working to design a duel pll clocking scheme and I am playing around with Ti's PLLatinum software and ADI's ADIsimPLL software. In order to design the first PLL which uses a VCXO as the oscillator I need to know certain parameters of the VCXO. The first parameter I need to know is the tuning sensitivity (Kvco) in MHz/V.
Using the above datasheet as an example. I am given the sensitivity in ppm/V. To convert the ppm/V to MHz/V would I simply multiply my the VCXO's intended frequency, 100MHz in this case, and divide by 10^6? Giving me a sensitivity of 0.0025 MHz / V?
I also need to know the VCO capacitance. The datasheet give me a load capacitance, but is that the same capacaitance the PLL softwares are asking for? It doesn't seem right using the capacitance from the VCXO output characteristics as the VCOcap. Especially since the ADI software shows that capacitance at the input of the VCO.
Lastly. All of the clocks I need to generate share 100 MHz has their least common factor, so i planned on the first pll in the duel pll system to produce 100 MHz. Is there any issues using a 100 MHz reference to try and lock my 100 MHz VCXO to? Would it be better to use a different reference frequency?
Thanks in advance,
Sami