PLL design: Basic problem

[umesh49]

Hi,
I am trying to design a PLL which could be tuned for less than 500kHz. I did not get any PLL which could work for less than 4 MHz, so decide to make my own PLL by using the combination of microprocessor ADC input and timer out as VCO. Now problem I am facing is to how to set the gain and bandwidth for this VCO. Other confusion I got is how this VCO should behave once input frequency will go beyond the bandwidth range. Can any one please help me regarding this?

Regards,
Umesh

 

[karesz]

Eventuelly:
IC VCO beside CD4046 and LM566...?:

K.

 

[umesh49]

Thanks..
I have ordered CD40406 and will check if it is going to work for me.
I got one curiosity about how VCO behaves if input voltage is so much to force it to operate beyond the bandwidth range. Could any body please help me to understand this?