PLL design and simulations

[cretu]

philips pll 18/30

Hi all,

I would really appreciate if anyone can give me any hints about how to start designing/simulating a PLL(VCo based)

thanks

Dan

 

[plishkin@zarya-k.ru]

pll design philips

You can take a look to:

**broken link removed**

PLL basic princeples descrabed,
Mathcad programs provaded.

 

[electronrancher]

ne564 jitter schematic

i say go read books! a nice source floating around here is "Phase Lock Techniques" which is very interesting if you only want to do math and are too afraid to go design circuits!

i will scan off some good stuff for you, but it may be time for you to build your ee library. along with the paul gray chapter on the classic 560 pll, johns & martin i think, and razavi both contribute heavy chapters on pll.

it's fun stuff - try to work thru this chapter on the 560, then you can go look at phillips 56x series datasheets, which all contain a rough schematic. example is the NE564, page 6. **broken link removed**

learn a couple of tricks from those philips datasheets, and i think you know enough about pll blocks to consider expanding to your own design. wireless pll's are of course a couple more chapters later..
what do you do - are you a student?

 

[electronrancher]

pll-design,programme

one note - that chip analysis starts on page 735. i gave you the oscillator analysis too because it's weird if you haven't built vco's before.. also, the 560 schematic on p736/737 overlaps a little by the "input" to the pd. i did this so you're sure you are not missing anything because of my bad scan.. haha


hey cretu, once you have hacked the 560, start bringing the 564 blocks in from the philips datasheets. philips app notes give a 564 analysis in **broken link removed**

the EC table in the 564 datasheet says 45-60mA, so we can count thru the branches to find rough estimates of the bias levels compared to our old friend the 560...

go ahead and pspice these using 3904 and 3906, and you will only have to change resistors to match the bias levels to the 56x.

next, feel free to build the blocks with 3904 & 3906 on breadboards. use the new resistor values found from spice, but don't expect it to be as "perfect" as spice! (matching is bad in discretes..)
you can hand-match the diff pair transistors to get a pretty good circuit (seems great at 12v, bad at 5.0v).. but that's OK, it works.

from here, transition into an ic design is easy - matching will be so good, integrated circuit will seem almost perfect when you finally get it.

johns & martin book is at work, so i will scan their info next week. anything else?

 

[cherrycen]

circuit 560 pll

any one can tell how fast the non-lc tank kind of vco
can run

 

[shiowjyh]

180Mhz, and jitter is around 0.7ns at 3.3v power supply.
Base on 0.25um process...

Regards,

 

[cretu]

thanks for all your answers. i have read some articles and I'll just start reading what you gave me. If somebody needs files, I can share some. I have another question: is there any site that can allow me to download books ?

Thnaks

 

[khouly]

u can visit


www.circuitsage.com
u will find many articles about PLL
and the design of VCO

 

[tlihu]

u can visit


www.circuitsage.com
u will find many articles about PLL
and the design of VCO

The site is good. However, many article links seem to be dead. :evil:

 

[lguancho]

The PLL deanbook from National Semiconductor is a non-printable version. You can get a printable version from electroda ebook section.

Alternatively, download the original file from Nation Semiconductor, and use any pdf password remover program to remove the password.

For PLL design and simulation, you can download a design program from Analog Device website. AD has a couple of more updated PLL design app notes.