PLL circuit sensitive to supply voltage

[yellowperil]

pll circuit design

Hi,

I wish to know if there is any other circuit in PLL which is sensitive to supply voltage apart from VCO.

As I have an problem with my PLL as it is only able to lock back after a long time ( ~ 5minutes) or if I reduce the VCO supply voltage. Do you guys have any idea of which circuit which might possible cause this problem?

BTW, the PLL is combination of PLL and CDR block.

Thanks.

 

[yellowperil]

supply insensitive pll design

Hope that this can give a clearer picture and advice from you guys.

Initially my PLL can lock to the reference clock (160MHz) using PFD and weaker Charge Pump. After lock to reference clock, the PLL switch to the Phase Detector and stronger Charge Pump. During this time, some mismatch in the input data, cause the PLL to increase its frequency until it is clamped by VCO max operating limit, 250MHz (which is VCO supply voltage). When switch back to the PFD circuit when VCO operate at 250MHz, it is only able to lock back after a long period.

Do you guys have any idea of which circuit which may potentially cause this to happen. Thanks.

 

[dick_freebird]

pll circuit

Charge pump leakage ("stronger" = "leakier")? could be pushing
the loop out of lock; transient misbehavior in switching all that
stuff between modes, might introduce a large charge-slug, a
design "oops" might introduce a phase inversion or skew, etc.
Changing charge pump strength might make the loop filter go
unstable. Loop amplifiers with non-rail-to-rail input range might
show phase inversion or input pair choke-off if the pump node
swings too wide.

Recommend you break the loop after capturing the pump and
VCO control node voltages aboutt the point of switchover, and
try to pare down the possibilities rather than collecting a whole
basket of conjecture.